Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a0e42d16 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.19.227 into android-4.19-stable 



Changes in 4.19.227
	drm/i915: Flush TLBs before releasing backing store
	net: bridge: clear bridge's private skb space on xmit
	select: Fix indefinitely sleeping task in poll_schedule_timeout()
	drm/vmwgfx: Fix stale file descriptors on failed usercopy
	Linux 4.19.227

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I6c614263af5682f536780b71e61b7b19710c5e6b
parents ee259c6c f4b1bd6d

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 226

SUBLEVEL = 227

EXTRAVERSION =

NAME = "People's Front"

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1595,6 +1595,8 @@ struct drm_i915_private { 


	struct intel_uncore uncore;



	struct mutex tlb_invalidate_lock;



	struct i915_virtual_gpu vgpu;



	struct intel_gvt *gvt;

drivers/gpu/drm/i915/i915_gem.c

+83 −0
Original line number Diff line number Diff line
@@ -2446,6 +2446,78 @@ static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) 
	rcu_read_unlock();

}



struct reg_and_bit {

	i915_reg_t reg;

	u32 bit;

};



static struct reg_and_bit

get_reg_and_bit(const struct intel_engine_cs *engine,

		const i915_reg_t *regs, const unsigned int num)

{

	const unsigned int class = engine->class;

	struct reg_and_bit rb = { .bit = 1 };



	if (WARN_ON_ONCE(class >= num || !regs[class].reg))

		return rb;



	rb.reg = regs[class];

	if (class == VIDEO_DECODE_CLASS)

		rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */



	return rb;

}



static void invalidate_tlbs(struct drm_i915_private *dev_priv)

{

	static const i915_reg_t gen8_regs[] = {

		[RENDER_CLASS]                  = GEN8_RTCR,

		[VIDEO_DECODE_CLASS]            = GEN8_M1TCR, /* , GEN8_M2TCR */

		[VIDEO_ENHANCEMENT_CLASS]       = GEN8_VTCR,

		[COPY_ENGINE_CLASS]             = GEN8_BTCR,

	};

	const unsigned int num = ARRAY_SIZE(gen8_regs);

	const i915_reg_t *regs = gen8_regs;

	struct intel_engine_cs *engine;

	enum intel_engine_id id;



	if (INTEL_GEN(dev_priv) < 8)

		return;



	GEM_TRACE("\n");



	assert_rpm_wakelock_held(dev_priv);



	mutex_lock(&dev_priv->tlb_invalidate_lock);

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	for_each_engine(engine, dev_priv, id) {

		/*

		 * HW architecture suggest typical invalidation time at 40us,

		 * with pessimistic cases up to 100us and a recommendation to

		 * cap at 1ms. We go a bit higher just in case.

		 */

		const unsigned int timeout_us = 100;

		const unsigned int timeout_ms = 4;

		struct reg_and_bit rb;



		rb = get_reg_and_bit(engine, regs, num);

		if (!i915_mmio_reg_offset(rb.reg))

			continue;



		I915_WRITE_FW(rb.reg, rb.bit);

		if (__intel_wait_for_register_fw(dev_priv,

						 rb.reg, rb.bit, 0,

						 timeout_us, timeout_ms,

						 NULL))

			DRM_ERROR_RATELIMITED("%s TLB invalidation did not complete in %ums!\n",

					      engine->name, timeout_ms);

	}



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	mutex_unlock(&dev_priv->tlb_invalidate_lock);

}



static struct sg_table *

__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)

{
@@ -2475,6 +2547,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) 
	__i915_gem_object_reset_page_iter(obj);

	obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;



	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {

		struct drm_i915_private *i915 = to_i915(obj->base.dev);



		if (intel_runtime_pm_get_if_in_use(i915)) {

			invalidate_tlbs(i915);

			intel_runtime_pm_put(i915);

		}

	}



	return pages;

}
@@ -5792,6 +5873,8 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv) 


	spin_lock_init(&dev_priv->fb_tracking.lock);



	mutex_init(&dev_priv->tlb_invalidate_lock);



	err = i915_gemfs_init(dev_priv);

	if (err)

		DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n", err);

drivers/gpu/drm/i915/i915_gem_object.h

+1 −0
Original line number Diff line number Diff line
@@ -136,6 +136,7 @@ struct drm_i915_gem_object { 
	 * activity?

	 */

#define I915_BO_ACTIVE_REF 0

#define I915_BO_WAS_BOUND_BIT    1



	/*

	 * Is the object to be mapped as read-only to the GPU

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -2431,6 +2431,12 @@ enum i915_power_well_id { 
#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)

#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)



#define GEN8_RTCR	_MMIO(0x4260)

#define GEN8_M1TCR	_MMIO(0x4264)

#define GEN8_M2TCR	_MMIO(0x4268)

#define GEN8_BTCR	_MMIO(0x426c)

#define GEN8_VTCR	_MMIO(0x4270)



#if 0

#define PRB0_TAIL	_MMIO(0x2030)

#define PRB0_HEAD	_MMIO(0x2034)