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Commit a0c3bf0f authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Update clk with od setting when set power state 



This can fix the issue resume from S3, the user's OD setting
were reverted to default.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 88de542e

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+15 −0
Original line number Diff line number Diff line
@@ -3259,10 +3259,25 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 
{

	int result = 0;

	struct vega10_hwmgr *data = hwmgr->backend;

	struct vega10_dpm_table *dpm_table = &data->dpm_table;

	struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;

	struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;

	int count;



	if (!data->need_update_dpm_table)

		return 0;



	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {

		for (count = 0; count < dpm_table->gfx_table.count; count++)

			dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;

	}



	odn_clk_table = &odn_table->vdd_dep_on_mclk;

	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {

		for (count = 0; count < dpm_table->mem_table.count; count++)

			dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;

	}



	if (data->need_update_dpm_table &

			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {

		result = vega10_populate_all_graphic_levels(hwmgr);