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Commit a0a6d4ff authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsi: add support for gpio elements on CHV 



Add support for CHV gpio programming in DSI gpio elements.

v2: Overhaul macros according to Ville's review.

v3: Address Ville's review:
 - swap E and SE gpio ranges
 - add a note about max SE index
 - use GPO, not HIZ
 - swap cfg0 and cfg1

v4: fix port for dsi sequence versions 1 and 2

[Rewritten by Jani, based on earlier work by Yogesh and Deepak.]

Signed-off-by: default avatarYogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: default avatarDeepak M <m.deepak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/bdaaf9915a5005305b31bb26cf619a5a82472f2a.1461666263.git.jani.nikula@intel.com
parent 4b541efe

drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

+70 −0
Original line number Diff line number Diff line
@@ -95,6 +95,24 @@ static struct gpio_map vlv_gpio_table[] = { 
	{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },

};



#define CHV_GPIO_IDX_START_N		0

#define CHV_GPIO_IDX_START_E		73

#define CHV_GPIO_IDX_START_SW		100

#define CHV_GPIO_IDX_START_SE		198



#define CHV_VBT_MAX_PINS_PER_FMLY	15



#define CHV_GPIO_PAD_CFG0(f, i)		(0x4400 + (f) * 0x400 + (i) * 8)

#define  CHV_GPIO_GPIOEN		(1 << 15)

#define  CHV_GPIO_GPIOCFG_GPIO		(0 << 8)

#define  CHV_GPIO_GPIOCFG_GPO		(1 << 8)

#define  CHV_GPIO_GPIOCFG_GPI		(2 << 8)

#define  CHV_GPIO_GPIOCFG_HIZ		(3 << 8)

#define  CHV_GPIO_GPIOTXSTATE(state)	((!!(state)) << 1)



#define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)

#define  CHV_GPIO_CFGLOCK		(1 << 31)



static inline enum port intel_dsi_seq_port_to_port(u8 port)

{

	return port ? PORT_C : PORT_A;
@@ -232,6 +250,56 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 
	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_exec_gpio(struct drm_i915_private *dev_priv,

			  u8 gpio_source, u8 gpio_index, bool value)

{

	u16 cfg0, cfg1;

	u16 family_num;

	u8 port;



	if (dev_priv->vbt.dsi.seq_version >= 3) {

		if (gpio_index >= CHV_GPIO_IDX_START_SE) {

			/* XXX: it's unclear whether 255->57 is part of SE. */

			gpio_index -= CHV_GPIO_IDX_START_SE;

			port = CHV_IOSF_PORT_GPIO_SE;

		} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {

			gpio_index -= CHV_GPIO_IDX_START_SW;

			port = CHV_IOSF_PORT_GPIO_SW;

		} else if (gpio_index >= CHV_GPIO_IDX_START_E) {

			gpio_index -= CHV_GPIO_IDX_START_E;

			port = CHV_IOSF_PORT_GPIO_E;

		} else {

			port = CHV_IOSF_PORT_GPIO_N;

		}

	} else {

		/* XXX: The spec is unclear about CHV GPIO on seq v2 */

		if (gpio_source != 0) {

			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);

			return;

		}



		if (gpio_index >= CHV_GPIO_IDX_START_E) {

			DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",

				      gpio_index);

			return;

		}



		port = CHV_IOSF_PORT_GPIO_N;

	}



	family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;

	gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;



	cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);

	cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);



	mutex_lock(&dev_priv->sb_lock);

	vlv_iosf_sb_write(dev_priv, port, cfg1, 0);

	vlv_iosf_sb_write(dev_priv, port, cfg0,

			  CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value));

	mutex_unlock(&dev_priv->sb_lock);

}



static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)

{

	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -255,6 +323,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 


	if (IS_VALLEYVIEW(dev_priv))

		vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);

	else if (IS_CHERRYVIEW(dev_priv))

		chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);

	else

		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");