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Commit a03a6e42 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add support for dcvs nodes for lagoon target"

parents e950d9d1 c8ce5494

qcom/lagoon.dtsi

+340 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ 
#include <dt-bindings/soc/qcom,ipcc.h>

#include <dt-bindings/msm/msm-bus-ids.h>



#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}



/ {

	model = "Qualcomm Technologies, Inc. Lagoon";

	compatible = "qcom,lagoon";
@@ -1858,6 +1861,343 @@ 
		qcom,smem-states = <&npu_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";

	};



	llcc_pmu: llcc-pmu@90cc000 {

		compatible = "qcom,llcc-pmu-ver1";

		reg = <0x090cc000 0x300>;

		reg-names = "lagg-base";

	};



	llcc_bw_opp_table: llcc-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */

		BW_OPP_ENTRY( 300, 16); /*  4577 MB/s */

		BW_OPP_ENTRY( 466, 16); /*  7110 MB/s */

		BW_OPP_ENTRY( 600, 16); /*  9155 MB/s */

		BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */

		BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */

		BW_OPP_ENTRY(1066, 16); /* 16265 MB/s */

	};



	suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(   0, 16); /*     0 MB/s */

		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */

		BW_OPP_ENTRY( 300, 16); /*  4577 MB/s */

		BW_OPP_ENTRY( 466, 16); /*  7110 MB/s */

		BW_OPP_ENTRY( 600, 16); /*  9155 MB/s */

		BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */

		BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */

		BW_OPP_ENTRY(1066, 16); /* 16265 MB/s */

	};



	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x90B6300 0x300>, <0x090B6200 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_cpu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY( 200, 4); /*  762 MB/s */

		BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */

		BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */

		BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */

		BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */

		BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */

		BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */

		BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */

		BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */

		BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */

		BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */

	};



	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x90cd000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(   0, 4); /*    0 MB/s */

		BW_OPP_ENTRY( 200, 4); /*  762 MB/s */

		BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */

		BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */

		BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */

		BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */

		BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */

		BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */

		BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */

		BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */

		BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */

		BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */

	};



	npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;

		operating-points-v2 = <&suspendable_llcc_bw_opp_table>;

	};



	npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@9960300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00060400 0x300>, <0x00060300 0x200>;

		reg-names = "base", "global_base";

		clocks = <&gcc RPMH_CXO_CLK>,

				<&gcc GCC_NPU_BWMON_DMA_CFG_AHB_CLK>,

				<&gcc GCC_NPU_BWMON_AXI_CLK>;

		clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,msm_bus = <154 512>;

		qcom,msm_bus_name = "npu_bwmon_cdsp";

		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_npu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

	};



	npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@90CE000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x90CE000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

	};



	npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00070300 0x300>, <0x00070200 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&gcc RPMH_CXO_CLK>,

				<&gcc GCC_NPU_BWMON_DSP_CFG_AHB_CLK>,

				<&gcc GCC_NPU_BWMON_AXI_CLK>;

		clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,msm_bus = <154 512>;

		qcom,msm_bus_name = "npu_bwmon_cdsp";

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npudsp_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;



		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_l3>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =

				<  672000  300000000 >,

				<  940800  556800000 >,

				< 1228800  806400000 >,

				< 1459200  940800000 >,

				< 1728000 1420000000 >;

		};



		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				< 1228800 MHZ_TO_MBPS(300, 16) >,

				< 1459200 MHZ_TO_MBPS(466, 16) >,

				< 1728000 MHZ_TO_MBPS(600, 16) >;

		};



		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 4) >,

				<  940800 MHZ_TO_MBPS( 451, 4) >,

				< 1228800 MHZ_TO_MBPS( 547, 4) >,

				< 1459200 MHZ_TO_MBPS( 768, 4) >,

				< 1728000 MHZ_TO_MBPS(1017, 4) >;

		};



		cpu0_computemon: qcom,cpu0-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 4) >,

				< 1228800 MHZ_TO_MBPS( 451, 4) >,

				< 1459200 MHZ_TO_MBPS( 547, 4) >,

				< 1728000 MHZ_TO_MBPS( 768, 4) >;

		};

	};



	cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu6_memlat_cpugrp: qcom,cpu6-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU6 &CPU7>;



		cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6 &CPU7>;

			qcom,target-dev = <&cpu6_l3>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =

				<  940800  556800000 >,

				< 1228800  806400000 >,

				< 1708800 1190400000 >,

				< 1900800 1382400000 >,

				< 2323200 1420000000 >;

		};



		cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6 &CPU7>;

			qcom,target-dev = <&cpu6_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 16) >,

				<  940800 MHZ_TO_MBPS( 466, 16) >,

				< 1228000 MHZ_TO_MBPS( 600, 16) >,

				< 1708800 MHZ_TO_MBPS( 806, 16) >,

				< 2350000 MHZ_TO_MBPS( 933, 16) >,

				< 3000000 MHZ_TO_MBPS(1066, 16) >;

		};



		cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6 &CPU7>;

			qcom,target-dev = <&cpu6_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 451, 4) >,

				<  940800 MHZ_TO_MBPS( 547, 4) >,

				< 1228000 MHZ_TO_MBPS(1017, 4) >,

				< 1708800 MHZ_TO_MBPS(1555, 4) >,

				< 2350000 MHZ_TO_MBPS(1804, 4) >,

				< 3000000 MHZ_TO_MBPS(2092, 4) >;

		};



		cpu6_computemon: qcom,cpu6-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU6 &CPU7>;

			qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 4) >,

				< 1228800 MHZ_TO_MBPS( 547, 4) >,

				< 1516800 MHZ_TO_MBPS( 768, 4) >,

				< 1708800 MHZ_TO_MBPS(1017, 4) >,

				< 2350000 MHZ_TO_MBPS(1804, 4) >,

				< 3000000 MHZ_TO_MBPS(2092, 4) >;

		};

	};

};



#include "lagoon-gdsc.dtsi"