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Commit a01ef59e authored by Pratyush Anand's avatar Pratyush Anand Committed by Bjorn Helgaas
Browse files

PCI: designware: Add dw_pcie prefix before cfg_read/write 



The cfg_read/write functions are DesignWare-specific.  Add dw_pcie prefix
to avoid collision in global name space.

Tested-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarPratyush Anand <pratyush.anand@st.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: default avatarJingoo Han <jg1.han@samsung.com>
parent ca165892

drivers/pci/host/pci-exynos.c

+3 −2
Original line number Diff line number Diff line
@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_r_mode(pp, true);

	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);

	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);

	exynos_pcie_sideband_dbi_r_mode(pp, false);

	return ret;

}
@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_w_mode(pp, true);

	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);

	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),

			where, size, val);

	exynos_pcie_sideband_dbi_w_mode(pp, false);

	return ret;

}

drivers/pci/host/pcie-designware.c

+14 −9
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 
	return sys->private_data;

}



int cfg_read(void __iomem *addr, int where, int size, u32 *val)

int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)

{

	*val = readl(addr);
@@ -88,7 +88,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val) 
	return PCIBIOS_SUCCESSFUL;

}



int cfg_write(void __iomem *addr, int where, int size, u32 val)

int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)

{

	if (size == 4)

		writel(val, addr);
@@ -126,7 +126,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->rd_own_conf)

		ret = pp->ops->rd_own_conf(pp, where, size, val);

	else

		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);

		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,

				size, val);



	return ret;

}
@@ -139,8 +140,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->wr_own_conf)

		ret = pp->ops->wr_own_conf(pp, where, size, val);

	else

		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,

				val);

		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,

				size, val);



	return ret;

}
@@ -574,11 +575,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	if (bus->parent->number == pp->root_bus_nr) {

		dw_pcie_prog_viewport_cfg0(pp, busdev);

		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);

		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,

				val);

		dw_pcie_prog_viewport_mem_outbound(pp);

	} else {

		dw_pcie_prog_viewport_cfg1(pp, busdev);

		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);

		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,

				val);

		dw_pcie_prog_viewport_io_outbound(pp);

	}
@@ -597,11 +600,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	if (bus->parent->number == pp->root_bus_nr) {

		dw_pcie_prog_viewport_cfg0(pp, busdev);

		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);

		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,

				val);

		dw_pcie_prog_viewport_mem_outbound(pp);

	} else {

		dw_pcie_prog_viewport_cfg1(pp, busdev);

		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);

		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,

				val);

		dw_pcie_prog_viewport_io_outbound(pp);

	}

drivers/pci/host/pcie-designware.h

+2 −2
Original line number Diff line number Diff line
@@ -66,8 +66,8 @@ struct pcie_host_ops { 
	void (*host_init)(struct pcie_port *pp);

};



int cfg_read(void __iomem *addr, int where, int size, u32 *val);

int cfg_write(void __iomem *addr, int where, int size, u32 val);

int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);

int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);

void dw_handle_msi_irq(struct pcie_port *pp);

void dw_pcie_msi_init(struct pcie_port *pp);

int dw_pcie_link_up(struct pcie_port *pp);