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Commit 9ffb7a6d authored by Ilija Hadzic's avatar Ilija Hadzic Committed by Alex Deucher
Browse files

drm/radeon: factor out cs_next_is_pkt3_nop function 



Once we factored out radeon_cs_packet_parse function,
evergreen_cs_next_is_pkt3_nop and r600_cs_next_is_pkt3_nop
functions became identical, so they can be factored out
into a common function.

Signed-off-by: default avatarIlija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: default avatarMarek Olšák <maraeo@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c38f34b5

drivers/gpu/drm/radeon/evergreen_cs.c

+1 −22
Original line number Diff line number Diff line
@@ -1054,27 +1054,6 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 
	return 0;

}



/**

 * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP

 * @p:		structure holding the parser context.

 *

 * Check if the next packet is a relocation packet3.

 **/

static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)

{

	struct radeon_cs_packet p3reloc;

	int r;



	r = radeon_cs_packet_parse(p, &p3reloc, p->idx);

	if (r) {

		return false;

	}

	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {

		return false;

	}

	return true;

}



/**

 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet

 * @parser:		parser structure holding parsing context.
@@ -2464,7 +2443,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 


				if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&

				    !mip_address &&

				    !evergreen_cs_packet_next_is_pkt3_nop(p)) {

				    !radeon_cs_packet_next_is_pkt3_nop(p)) {

					/* MIP_ADDRESS should point to FMASK for an MSAA texture.

					 * It should be 0 if FMASK is disabled. */

					moffset = 0;

drivers/gpu/drm/radeon/r600_cs.c

+4 −26
Original line number Diff line number Diff line
@@ -876,28 +876,6 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 
	return 0;

}



/**

 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc

 * @parser:		parser structure holding parsing context.

 *

 * Check next packet is relocation packet3, do bo validation and compute

 * GPU offset using the provided start.

 **/

static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)

{

	struct radeon_cs_packet p3reloc;

	int r;



	r = radeon_cs_packet_parse(p, &p3reloc, p->idx);

	if (r) {

		return 0;

	}

	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {

		return 0;

	}

	return 1;

}



/**

 * r600_cs_packet_next_vline() - parse userspace VLINE packet

 * @parser:		parser structure holding parsing context.
@@ -1108,7 +1086,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
		break;

	case R_028010_DB_DEPTH_INFO:

		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&

		    r600_cs_packet_next_is_pkt3_nop(p)) {

		    radeon_cs_packet_next_is_pkt3_nop(p)) {

			r = r600_cs_packet_next_reloc(p, &reloc);

			if (r) {

				dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1209,7 +1187,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case R_0280B8_CB_COLOR6_INFO:

	case R_0280BC_CB_COLOR7_INFO:

		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&

		     r600_cs_packet_next_is_pkt3_nop(p)) {

		     radeon_cs_packet_next_is_pkt3_nop(p)) {

			r = r600_cs_packet_next_reloc(p, &reloc);

			if (r) {

				dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
@@ -1273,7 +1251,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case R_0280F8_CB_COLOR6_FRAG:

	case R_0280FC_CB_COLOR7_FRAG:

		tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;

		if (!r600_cs_packet_next_is_pkt3_nop(p)) {

		if (!radeon_cs_packet_next_is_pkt3_nop(p)) {

			if (!track->cb_color_base_last[tmp]) {

				dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);

				return -EINVAL;
@@ -1304,7 +1282,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case R_0280D8_CB_COLOR6_TILE:

	case R_0280DC_CB_COLOR7_TILE:

		tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;

		if (!r600_cs_packet_next_is_pkt3_nop(p)) {

		if (!radeon_cs_packet_next_is_pkt3_nop(p)) {

			if (!track->cb_color_base_last[tmp]) {

				dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);

				return -EINVAL;

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -1975,6 +1975,8 @@ static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 
int radeon_cs_packet_parse(struct radeon_cs_parser *p,

			   struct radeon_cs_packet *pkt,

			   unsigned idx);

bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);





#include "radeon_object.h"

drivers/gpu/drm/radeon/radeon_cs.c

+21 −0
Original line number Diff line number Diff line
@@ -695,3 +695,24 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p, 
	}

	return 0;

}



/**

 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP

 * @p:		structure holding the parser context.

 *

 * Check if the next packet is NOP relocation packet3.

 **/

bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)

{

	struct radeon_cs_packet p3reloc;

	int r;



	r = radeon_cs_packet_parse(p, &p3reloc, p->idx);

	if (r)

		return false;

	if (p3reloc.type != RADEON_PACKET_TYPE3)

		return false;

	if (p3reloc.opcode != RADEON_PACKET3_NOP)

		return false;

	return true;

}

drivers/gpu/drm/radeon/radeon_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -3717,4 +3717,6 @@ 
#define RADEON_PACKET_TYPE2 2

#define RADEON_PACKET_TYPE3 3



#define RADEON_PACKET3_NOP 0x10



#endif