Merge "msm: kgsl: Configure LLC based on type of mmu" (9faae36d) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/msm/adreno_a6xx.c

+14 −10

Original line number	Diff line number	Diff line
		@@ -1281,23 +1281,22 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev)
		uint32_t gpu_scid;
		uint32_t gpu_cntl1_val = 0;
		int i;
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct kgsl_mmu *mmu = &device->mmu;

		gpu_scid = adreno_llc_get_scid(adreno_dev->gpu_llc_slice);
		for (i = 0; i < A6XX_LLC_NUM_GPU_SCIDS; i++)
		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)
		\| gpu_scid;

		if (adreno_is_a640_family(adreno_dev) \|\|
		adreno_is_a612(adreno_dev) \|\|
		adreno_is_a650_family(adreno_dev)) {
		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,
		if (mmu->subtype == KGSL_IOMMU_SMMU_V500)
		kgsl_regrmw(device, A6XX_GBIF_SCACHE_CNTL1,
		A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);
		} else {
		else
		adreno_cx_misc_regrmw(adreno_dev,
		A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,
		A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);
		}
		}

		/*
		* a6xx_llc_configure_gpuhtw_scid() - Program the SCID for GPU pagetables
		@@ -1306,12 +1305,14 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev)
		static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev)
		{
		uint32_t gpuhtw_scid;
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct kgsl_mmu *mmu = &device->mmu;

		/*
		* On A640, the GPUHTW SCID is configured via a NoC override in the
		* XBL image.
		* On SMMU-v500, the GPUHTW SCID is configured via a NoC override in
		* the XBL image.
		*/
		if (adreno_is_a640_family(adreno_dev) \|\| adreno_is_a612(adreno_dev))
		if (mmu->subtype == KGSL_IOMMU_SMMU_V500)
		return;

		gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);
		@@ -1328,11 +1329,14 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev)
		*/
		static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct kgsl_mmu *mmu = &device->mmu;

		/*
		* Attributes override through GBIF is not supported with MMU-500.
		* Attributes are used as configured through SMMU pagetable entries.
		*/
		if (adreno_is_a640_family(adreno_dev) \|\| adreno_is_a612(adreno_dev))
		if (mmu->subtype == KGSL_IOMMU_SMMU_V500)
		return;

		/*

drivers/gpu/msm/kgsl_iommu.c

+9 −3

Original line number	Diff line number	Diff line
		@@ -1179,8 +1179,7 @@ void _enable_gpuhtw_llc(struct kgsl_mmu mmu, struct kgsl_iommu_pt iommu_pt)
		return;

		/* Domain attribute to enable system cache for GPU pagetable walks */
		if (adreno_is_a650_family(adreno_dev) \|\| adreno_is_a640(adreno_dev) \|\|
		adreno_is_a612(adreno_dev))
		if (mmu->subtype == KGSL_IOMMU_SMMU_V500)
		ret = iommu_domain_set_attr(iommu_pt->domain,
		DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable);
		else
		@@ -2639,7 +2638,7 @@ static int _kgsl_iommu_probe(struct kgsl_device *device,
		u32 reg_val[2];
		int i = 0;
		struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
		struct device_node *child;
		struct device_node child, iommu_node = NULL;
		struct platform_device *pdev = of_find_device_by_node(node);

		memset(iommu, 0, sizeof(*iommu));
		@@ -2699,8 +2698,15 @@ static int _kgsl_iommu_probe(struct kgsl_device *device,
		ret = _kgsl_iommu_cb_probe(device, iommu, child);
		if (ret)
		return ret;

		if (!iommu_node)
		iommu_node = of_parse_phandle(child, "iommus", 0);
		}

		if (iommu_node &&
		of_device_is_compatible(iommu_node, "qcom,qsmmu-v500"))
		device->mmu.subtype = KGSL_IOMMU_SMMU_V500;

		return 0;
		}

drivers/gpu/msm/kgsl_mmu.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,8 @@ enum kgsl_mmutype {
		KGSL_MMU_TYPE_NONE
		};

		#define KGSL_IOMMU_SMMU_V500 1

		struct kgsl_pagetable {
		spinlock_t lock;
		struct kref refcount;
		@@ -140,6 +142,7 @@ struct kgsl_mmu_pt_ops {
		* struct kgsl_mmu - Master definition for KGSL MMU devices
		* @flags: MMU device flags
		* @type: Type of MMU that is attached
		* @subtype: Sub Type of MMU that is attached
		* @defaultpagetable: Default pagetable object for the MMU
		* @securepagetable: Default secure pagetable object for the MMU
		* @mmu_ops: Function pointers for the MMU sub-type
		@@ -151,6 +154,7 @@ struct kgsl_mmu_pt_ops {
		struct kgsl_mmu {
		unsigned long flags;
		enum kgsl_mmutype type;
		u32 subtype;
		struct kgsl_pagetable *defaultpagetable;
		struct kgsl_pagetable *securepagetable;
		const struct kgsl_mmu_ops *mmu_ops;