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Commit 9f999b41 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman
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staging: mt7621-pci: use pcie_[read|write] in [write|read]_config 



Instead of custom macros use pcie_read and pcie_write functions.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Tested-by: default avatarNeilBrown <neil@brown.name>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 52ed727c

drivers/staging/mt7621-pci/pci-mt7621.c

+32 −35
Original line number Original line Diff line number Diff line
@@ -240,41 +240,38 @@ struct pci_ops mt7621_pci_ops = { 
};

};





static void

static void

read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)

read_config(struct mt7621_pcie *pcie,

	    unsigned long bus, unsigned long dev,

	    unsigned long func, unsigned long reg, unsigned long *val)

{

{

	u32 address_reg, data_reg, address;

	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);





	address_reg = RALINK_PCI_CONFIG_ADDR;

	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);

	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;

	*val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);

	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);

	MV_WRITE(address_reg, address);

	MV_READ(data_reg, val);

	return;

}

}





static void

static void

write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)

write_config(struct mt7621_pcie *pcie,

	     unsigned long bus, unsigned long dev,

	     unsigned long func, unsigned long reg, unsigned long val)

{

{

	u32 address_reg, data_reg, address;

	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);





	address_reg = RALINK_PCI_CONFIG_ADDR;

	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);

	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;

	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);

	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);

	MV_WRITE(address_reg, address);

	MV_WRITE(data_reg, val);

	return;

}

}





int

int

pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

{

	struct mt7621_pcie *pcie = dev->bus->sysdata;

	u16 cmd;

	u16 cmd;

	u32 val;

	u32 val;

	int irq;

	int irq;





	if (dev->bus->number == 0) {

	if (dev->bus->number == 0) {

		write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);

		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);

		read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);

		read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);

		printk("BAR0 at slot %d = %x\n", slot, val);

		printk("BAR0 at slot %d = %x\n", slot, val);

	}

	}
@@ -572,13 +569,13 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
		bypass_pipe_rst();

		bypass_pipe_rst();

	set_phy_for_ssc();

	set_phy_for_ssc();





	read_config(0, 0, 0, 0x70c, &val);

	read_config(pcie, 0, 0, 0, 0x70c, &val);

	printk("Port 0 N_FTS = %x\n", (unsigned int)val);

	printk("Port 0 N_FTS = %x\n", (unsigned int)val);





	read_config(0, 1, 0, 0x70c, &val);

	read_config(pcie, 0, 1, 0, 0x70c, &val);

	printk("Port 1 N_FTS = %x\n", (unsigned int)val);

	printk("Port 1 N_FTS = %x\n", (unsigned int)val);





	read_config(0, 2, 0, 0x70c, &val);

	read_config(pcie, 0, 2, 0, 0x70c, &val);

	printk("Port 2 N_FTS = %x\n", (unsigned int)val);

	printk("Port 2 N_FTS = %x\n", (unsigned int)val);





	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);

	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -699,28 +696,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 




	switch (pcie_link_status) {

	switch (pcie_link_status) {

	case 7:

	case 7:

		read_config(0, 2, 0, 0x4, &val);

		read_config(pcie, 0, 2, 0, 0x4, &val);

		write_config(0, 2, 0, 0x4, val|0x4);

		write_config(pcie, 0, 2, 0, 0x4, val|0x4);

		read_config(0, 2, 0, 0x70c, &val);

		read_config(pcie, 0, 2, 0, 0x70c, &val);

		val &= ~(0xff)<<8;

		val &= ~(0xff)<<8;

		val |= 0x50<<8;

		val |= 0x50<<8;

		write_config(0, 2, 0, 0x70c, val);

		write_config(pcie, 0, 2, 0, 0x70c, val);

	case 3:

	case 3:

	case 5:

	case 5:

	case 6:

	case 6:

		read_config(0, 1, 0, 0x4, &val);

		read_config(pcie, 0, 1, 0, 0x4, &val);

		write_config(0, 1, 0, 0x4, val|0x4);

		write_config(pcie, 0, 1, 0, 0x4, val|0x4);

		read_config(0, 1, 0, 0x70c, &val);

		read_config(pcie, 0, 1, 0, 0x70c, &val);

		val &= ~(0xff)<<8;

		val &= ~(0xff)<<8;

		val |= 0x50<<8;

		val |= 0x50<<8;

		write_config(0, 1, 0, 0x70c, val);

		write_config(pcie, 0, 1, 0, 0x70c, val);

	default:

	default:

		read_config(0, 0, 0, 0x4, &val);

		read_config(pcie, 0, 0, 0, 0x4, &val);

		write_config(0, 0, 0, 0x4, val|0x4); //bus master enable

		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable

		read_config(0, 0, 0, 0x70c, &val);

		read_config(pcie, 0, 0, 0, 0x70c, &val);

		val &= ~(0xff)<<8;

		val &= ~(0xff)<<8;

		val |= 0x50<<8;

		val |= 0x50<<8;

		write_config(0, 0, 0, 0x70c, val);

		write_config(pcie, 0, 0, 0, 0x70c, val);

	}

	}





	err = mt7621_pci_parse_request_of_pci_ranges(pcie);

	err = mt7621_pci_parse_request_of_pci_ranges(pcie);