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Commit 9f7be893 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
40GbE Intel Wired LAN Driver Updates 2017-10-09

This series contains updates to i40e and i40evf only.

Jake fixes missed flag conversion from u64 to u32.  Fixes a deafult ITR
value issue where the driver defaults to an ITR value of half the
expected value (in terms of minimum microseconds between interrupts).  So
fix this by changing the default values to be calculated using the
ITR_REG_TO_USEC() macro which indicates that we are converting from the
register units into microseconds. Updates the drivers to bump the tail in
increments of 8 and double the number of descriptors we will bundle into
one tail bump when receiving.  With the recent kernel support for
enabling XPS and QoS at the same time, we no longer need to worry about
the number of traffic classes when enabling XPS.

Lihong converts the use of hash_for_each() to hash_for_each_safe() to
safely remove a hash entry.  Adds a check for the return value for
find_first_bit() in the case that it returns the size passed to search.

Alan fixes a bug in which filters are erroneously removed if they are
removed and then added again.  So make sure that when adding a filter, if
we find it already existed in our list, make sure it is not marked to be
removed.

Jayaprakash adds the retrying of PHY reads when the I2C is busy for a
maximum period of 500ms.

Rami fixes code comment typo.

Stefano Brivio simplifies the code by removing the use of a local
return code variable and simply return the results of the read function.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0349a86c 2c4d36b7

drivers/net/ethernet/intel/i40e/i40e.h

+2 −5
Original line number Diff line number Diff line
@@ -424,7 +424,7 @@ struct i40e_pf { 
#define I40E_HW_PORT_ID_VALID			BIT(17)

#define I40E_HW_RESTART_AUTONEG			BIT(18)



	u64 flags;

	u32 flags;

#define I40E_FLAG_RX_CSUM_ENABLED		BIT(0)

#define I40E_FLAG_MSI_ENABLED			BIT(1)

#define I40E_FLAG_MSIX_ENABLED			BIT(2)
@@ -949,9 +949,6 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 
	struct i40e_hw *hw = &pf->hw;

	u32 val;



	/* definitely clear the PBA here, as this function is meant to

	 * clean out all previous interrupts AND enable the interrupt

	 */

	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |

	      I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |

	      (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
@@ -960,7 +957,7 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 
}



void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);

void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);

void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);

int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);

int i40e_open(struct net_device *netdev);

int i40e_close(struct net_device *netdev);

drivers/net/ethernet/intel/i40e/i40e_common.c

+29 −13
Original line number Diff line number Diff line
@@ -1567,10 +1567,12 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 
	struct i40e_aq_desc desc;

	i40e_status status;

	u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);

	u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;



	if (!abilities)

		return I40E_ERR_PARAM;



	do {

		i40e_fill_default_direct_cmd_desc(&desc,

					       i40e_aqc_opc_get_phy_abilities);
@@ -1586,11 +1588,25 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 
			desc.params.external.param0 |=

			cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);



	status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,

				       cmd_details);

		status = i40e_asq_send_command(hw, &desc, abilities,

					       abilities_size, cmd_details);



		if (status)

			break;



	if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)

		if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {

			status = I40E_ERR_UNKNOWN_PHY;

			break;

		} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {

			usleep_range(1000, 2000);

			total_delay++;

			status = I40E_ERR_TIMEOUT;

		}

	} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&

		 (total_delay < max_delay));



	if (status)

		return status;



	if (report_init) {

		if (hw->mac.type ==  I40E_MAC_XL710 &&

drivers/net/ethernet/intel/i40e/i40e_main.c

+15 −21
Original line number Diff line number Diff line
@@ -2879,25 +2879,20 @@ static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) 
 **/

static void i40e_config_xps_tx_ring(struct i40e_ring *ring)

{

	struct i40e_vsi *vsi = ring->vsi;

	int cpu;



	if (!ring->q_vector || !ring->netdev)

		return;



	if ((vsi->tc_config.numtc <= 1) &&

	    !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state)) {

	/* We only initialize XPS once, so as not to overwrite user settings */

	if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state))

		return;



	cpu = cpumask_local_spread(ring->q_vector->v_idx, -1);

	netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu),

			    ring->queue_index);

}



	/* schedule our worker thread which will take care of

	 * applying the new filter changes

	 */

	i40e_service_event_schedule(vsi->back);

}



/**

 * i40e_configure_tx_ring - Configure a transmit ring context and rest

 * @ring: The Tx ring to configure
@@ -3030,7 +3025,7 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring) 
	if (hw->revision_id == 0)

		rx_ctx.lrxqthresh = 0;

	else

		rx_ctx.lrxqthresh = 2;

		rx_ctx.lrxqthresh = 1;

	rx_ctx.crcstrip = 1;

	rx_ctx.l2tsel = 1;

	/* this controls whether VLAN is stripped from inner headers */
@@ -3403,15 +3398,14 @@ void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) 
/**

 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0

 * @pf: board private structure

 * @clearpba: true when all pending interrupt events should be cleared

 **/

void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)

void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)

{

	struct i40e_hw *hw = &pf->hw;

	u32 val;



	val = I40E_PFINT_DYN_CTL0_INTENA_MASK   |

	      (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |

	      I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |

	      (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);



	wr32(hw, I40E_PFINT_DYN_CTL0, val);
@@ -3597,7 +3591,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) 
		for (i = 0; i < vsi->num_q_vectors; i++)

			i40e_irq_dynamic_enable(vsi, i);

	} else {

		i40e_irq_dynamic_enable_icr0(pf, true);

		i40e_irq_dynamic_enable_icr0(pf);

	}



	i40e_flush(&pf->hw);
@@ -3746,7 +3740,7 @@ static irqreturn_t i40e_intr(int irq, void *data) 
	wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);

	if (!test_bit(__I40E_DOWN, pf->state)) {

		i40e_service_event_schedule(pf);

		i40e_irq_dynamic_enable_icr0(pf, false);

		i40e_irq_dynamic_enable_icr0(pf);

	}



	return ret;
@@ -7694,7 +7688,7 @@ static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) 


/**

 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi

 * @type: VSI pointer

 * @vsi: VSI pointer

 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.

 *

 * On error: returns error code (negative)
@@ -8455,7 +8449,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf) 


	i40e_flush(hw);



	i40e_irq_dynamic_enable_icr0(pf, true);

	i40e_irq_dynamic_enable_icr0(pf);



	return err;

}
@@ -8983,8 +8977,8 @@ static int i40e_sw_init(struct i40e_pf *pf) 
		    I40E_FLAG_MSIX_ENABLED;



	/* Set default ITR */

	pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;

	pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;

	pf->rx_itr_default = I40E_ITR_RX_DEF;

	pf->tx_itr_default = I40E_ITR_TX_DEF;



	/* Depending on PF configurations, it is possible that the RSS

	 * maximum might end up larger than the available queues

drivers/net/ethernet/intel/i40e/i40e_nvm.c

+7 −13
Original line number Diff line number Diff line
@@ -311,13 +311,10 @@ static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 
static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,

					u16 offset, u16 *data)

{

	i40e_status ret_code = 0;



	if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)

		ret_code = i40e_read_nvm_word_aq(hw, offset, data);

	else

		ret_code = i40e_read_nvm_word_srctl(hw, offset, data);

	return ret_code;

		return i40e_read_nvm_word_aq(hw, offset, data);



	return i40e_read_nvm_word_srctl(hw, offset, data);

}



/**
@@ -331,7 +328,7 @@ static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw, 
i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,

			       u16 *data)

{

	i40e_status ret_code = 0;

	i40e_status ret_code;



	ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);

	if (ret_code)
@@ -446,13 +443,10 @@ static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw, 
					  u16 offset, u16 *words,

					  u16 *data)

{

	i40e_status ret_code = 0;



	if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)

		ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data);

	else

		ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);

	return ret_code;

		return i40e_read_nvm_buffer_aq(hw, offset, words, data);



	return i40e_read_nvm_buffer_srctl(hw, offset, words, data);

}



/**

drivers/net/ethernet/intel/i40e/i40e_txrx.c

+11 −4
Original line number Diff line number Diff line
@@ -1372,6 +1372,15 @@ bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 
	union i40e_rx_desc *rx_desc;

	struct i40e_rx_buffer *bi;



	/* Hardware only fetches new descriptors in cache lines of 8,

	 * essentially ignoring the lower 3 bits of the tail register. We want

	 * to ensure our tail writes are aligned to avoid unnecessary work. We

	 * can't simply round down the cleaned count, since we might fail to

	 * allocate some buffers. What we really want is to ensure that

	 * next_to_used + cleaned_count produces an aligned value.

	 */

	cleaned_count -= (ntu + cleaned_count) & 0x7;



	/* do nothing if no valid netdev defined */

	if (!rx_ring->netdev || !cleaned_count)

		return false;
@@ -2202,9 +2211,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr) 
	u32 val;



	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |

	      /* Don't clear PBA because that can cause lost interrupts that

	       * came in while we were cleaning/polling

	       */

	      I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |

	      (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |

	      (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
@@ -2241,7 +2248,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 


	/* If we don't have MSIX, then we only need to re-enable icr0 */

	if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {

		i40e_irq_dynamic_enable_icr0(vsi->back, false);

		i40e_irq_dynamic_enable_icr0(vsi->back);

		return;

	}