Loading drivers/clk/qcom/npucc-lagoon.c +10 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,10 @@ static const u32 crc_reg_val[] = { CRC_MND_CFG_SETTING, CRC_SID_FSM_CTRL_SETTING, }; static struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; /* 537.60MHz Configuration */ static struct alpha_pll_config npu_cc_pll0_config = { .l = 0x1C, Loading @@ -119,6 +123,8 @@ static struct alpha_pll_config npu_cc_pll0_config = { static struct clk_alpha_pll npu_cc_pll0 = { .offset = 0x0, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_cc_pll0_config, .clkr = { Loading Loading @@ -152,6 +158,8 @@ static struct alpha_pll_config npu_cc_pll1_config = { static struct clk_alpha_pll npu_cc_pll1 = { .offset = 0x400, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_cc_pll1_config, .clkr = { Loading Loading @@ -185,6 +193,8 @@ static struct alpha_pll_config npu_q6ss_pll_config = { static struct clk_alpha_pll npu_q6ss_pll = { .offset = 0x0, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_q6ss_pll_config, .clkr = { Loading Loading
drivers/clk/qcom/npucc-lagoon.c +10 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,10 @@ static const u32 crc_reg_val[] = { CRC_MND_CFG_SETTING, CRC_SID_FSM_CTRL_SETTING, }; static struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; /* 537.60MHz Configuration */ static struct alpha_pll_config npu_cc_pll0_config = { .l = 0x1C, Loading @@ -119,6 +123,8 @@ static struct alpha_pll_config npu_cc_pll0_config = { static struct clk_alpha_pll npu_cc_pll0 = { .offset = 0x0, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_cc_pll0_config, .clkr = { Loading Loading @@ -152,6 +158,8 @@ static struct alpha_pll_config npu_cc_pll1_config = { static struct clk_alpha_pll npu_cc_pll1 = { .offset = 0x400, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_cc_pll1_config, .clkr = { Loading Loading @@ -185,6 +193,8 @@ static struct alpha_pll_config npu_q6ss_pll_config = { static struct clk_alpha_pll npu_q6ss_pll = { .offset = 0x0, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .config = &npu_q6ss_pll_config, .clkr = { Loading