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Commit 9eb7aa89 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
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can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS 



In order to receive RTR frames in the non HW FIFO mode the RSS and EACEN bits
of the reg_ctrl2 have to be activated. As this has no side effect in the FIFO
mode, we do this unconditionally on cores with the reg_ctrl2.

Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 4bd888a8

drivers/net/can/flexcan.c

+11 −3
Original line number Diff line number Diff line
@@ -187,7 +187,8 @@ 
 */

#define FLEXCAN_QUIRK_BROKEN_ERR_STATE	BIT(1) /* [TR]WRN_INT not connected */

#define FLEXCAN_QUIRK_DISABLE_RXFG	BIT(2) /* Disable RX FIFO Global mask */

#define FLEXCAN_QUIRK_DISABLE_MECR	BIT(3) /* Disble Memory error detection */

#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS	BIT(3) /* Enable EACEN and RRS bit in ctrl2 */

#define FLEXCAN_QUIRK_DISABLE_MECR	BIT(4) /* Disble Memory error detection */



/* Structure of the message buffer */

struct flexcan_mb {
@@ -276,11 +277,12 @@ static const struct flexcan_devtype_data fsl_p1010_devtype_data = { 
static const struct flexcan_devtype_data fsl_imx28_devtype_data;



static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG,

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS,

};



static const struct flexcan_devtype_data fsl_vf610_devtype_data = {

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |

		FLEXCAN_QUIRK_DISABLE_MECR,

};



static const struct can_bittiming_const flexcan_bittiming_const = {
@@ -825,6 +827,12 @@ static int flexcan_chip_start(struct net_device *dev) 
	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);

	flexcan_write(reg_ctrl, &regs->ctrl);



	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {

		reg_ctrl2 = flexcan_read(&regs->ctrl2);

		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;

		flexcan_write(reg_ctrl2, &regs->ctrl2);

	}



	/* clear and invalidate all mailboxes first */

	for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {

		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,