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Commit 9e366ace authored by Prudhvi Yarlagadda's avatar Prudhvi Yarlagadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add GPI DMA and QUPv3 SE dt nodes for bengal 

Add GPI device tree nodes and QUPv3 SE dt nodes for SPI,
I2C, HSUART and console UART on bengal.

Change-Id: Ia037e30e12e367cbc274e308abb2ce09b11d6ace
parent 13ce652e

qcom/bengal-pinctrl.dtsi

+249 −0
Original line number Diff line number Diff line
@@ -144,5 +144,254 @@ 
				bias-disable;

			};

		};



		qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {

			qupv3_se4_2uart_active: qupv3_se4_2uart_active {

				mux {

					pins = "gpio12", "gpio13";

					function = "qup4";

				};



				config {

					pins = "gpio12", "gpio13";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {

				mux {

					pins = "gpio12", "gpio13";

					function = "gpio";

				};



				config {

					pins = "gpio12", "gpio13";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {

			qupv3_se3_ctsrx: qupv3_se3_ctsrx {

				mux {

					pins = "gpio8", "gpio11";

					function = "qup3";

				};



				config {

					pins = "gpio8", "gpio11";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se3_rts: qupv3_se3_rts {

				mux {

					pins = "gpio9";

					function = "qup3";

				};



				config {

					pins = "gpio9";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se3_tx: qupv3_se3_tx {

				mux {

					pins = "gpio10";

					function = "qup3";

				};



				config {

					pins = "gpio10";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {

			qupv3_se0_i2c_active: qupv3_se0_i2c_active {

				mux {

					pins = "gpio0", "gpio1";

					function = "qup0";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {

				mux {

					pins = "gpio0", "gpio1";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {

			qupv3_se1_i2c_active: qupv3_se1_i2c_active {

				mux {

					pins = "gpio4", "gpio5";

					function = "qup1";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {

				mux {

					pins = "gpio4", "gpio5";

					function = "gpio";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {

			qupv3_se2_i2c_active: qupv3_se2_i2c_active {

				mux {

					pins = "gpio6", "gpio7";

					function = "qup2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {

				mux {

					pins = "gpio6", "gpio7";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se0_spi_pins: qupv3_se0_spi_pins {

			qupv3_se0_spi_active: qupv3_se0_spi_active {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "qup0";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se1_spi_pins: qupv3_se1_spi_pins {

			qupv3_se1_spi_active: qupv3_se1_spi_active {

				mux {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					function = "qup1";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {

				mux {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					function = "gpio";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se5_spi_pins: qupv3_se5_spi_pins {

			qupv3_se5_spi_active: qupv3_se5_spi_active {

				mux {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					function = "qup5";

				};



				config {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {

				mux {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					function = "gpio";

				};



				config {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};

	};

};

qcom/bengal-qupv3.dtsi

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+205 −0
Original line number Diff line number Diff line 
#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/* QUPv3_0  wrapper  instance */

	qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x4ac0000 0x2000>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-bus-ids =

			<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,

			<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;

		qcom,vote-for-bw;

		iommus = <&apps_smmu 0xe3 0x0>;

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		qcom,iommu-dma = "atomic";

	};



	/* GPI Instance */

	gpi_dma0: qcom,gpi-dma@4a00000 {

		compatible = "qcom,gpi-dma";

		#address-cells = <5>;

		reg = <0x4a00000 0x60000>;

		reg-names = "gpi-top";

		interrupts = <0 335 0>, <0 336 0>, <0 337 0>, <0 338 0>,

			<0 339 0>, <0 340 0>, <0 341 0>, <0 342 0>,

			<0 343 0>, <0 344 0>;

		qcom,max-num-gpii = <10>;

		qcom,gpii-mask = <0xf>;

		qcom,ev-factor = <2>;

		iommus = <&apps_smmu 0xf6 0x0>;

		qcom,gpi-ee-offset = <0x10000>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		status = "ok";

	};



	/* Debug UART Instance */

	qupv3_se4_2uart: qcom,qup_uart@4a90000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x4a90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_active>;

		pinctrl-1 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* HS UART Instance */

	qupv3_se3_4uart: qcom,qup_uart@4a8c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4a8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,

						<&qupv3_se3_tx>;

		pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,

						<&qupv3_se3_tx>;

		interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};



	/* I2C Instance */

	qupv3_se0_i2c: i2c@4a80000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a80000 0x4000>;

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		dmas = <&gpi_dma0 0 0 3 64 0>,

			<&gpi_dma0 1 0 3 64 0>;

		dma-names = "tx", "rx";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_i2c_active>;

		pinctrl-1 = <&qupv3_se0_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* I2C Instance */

	qupv3_se1_i2c: i2c@4a84000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a84000 0x4000>;

		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		dmas = <&gpi_dma0 0 1 3 64 0>,

			<&gpi_dma0 1 1 3 64 0>;

		dma-names = "tx", "rx";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_i2c_active>;

		pinctrl-1 = <&qupv3_se1_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* I2C Instance */

	qupv3_se2_i2c: i2c@4a88000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a88000 0x4000>;

		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		dmas = <&gpi_dma0 0 2 3 64 0>,

			<&gpi_dma0 1 2 3 64 0>;

		dma-names = "tx", "rx";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_i2c_active>;

		pinctrl-1 = <&qupv3_se2_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* SPI Instance */

	qupv3_se0_spi: spi@4a80000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x4a80000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_spi_active>;

		pinctrl-1 = <&qupv3_se0_spi_sleep>;

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 0 1 64 0>,

			<&gpi_dma0 1 0 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	/* SPI Instance */

	qupv3_se1_spi: spi@4a84000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x4a84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_spi_active>;

		pinctrl-1 = <&qupv3_se1_spi_sleep>;

		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 1 1 64 0>,

			<&gpi_dma0 1 1 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	/* SPI Instance */

	qupv3_se5_spi: spi@4a94000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x4a94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_spi_active>;

		pinctrl-1 = <&qupv3_se5_spi_sleep>;

		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 5 1 64 0>,

			<&gpi_dma0 1 5 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};

};

qcom/bengal.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -1390,3 +1390,8 @@ 
#include "msm-arm-smmu-bengal.dtsi"

#include "bengal-regulator.dtsi"

#include "bengal-pinctrl.dtsi"

#include "bengal-qupv3.dtsi"



&qupv3_se4_2uart {

	status = "ok";

};