Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9dcd9acd authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller
Browse files

bnx2x: Prevent panic during DMAE timeout 



If chip enters a recovery flow just after the driver issues a DMAE request
the DMAE will timeout. Current code will cause a bnx2x_panic() as a result,
which means interface will no longer be usable (regardless of the recovery
results), as bnx2x_panic() is irreversible for the driver.

As this is a possible flow, the panic should be reached only when driver
is compiled with STOP_ON_ERROR.

Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a0d307b2

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+8 −0
Original line number Diff line number Diff line
@@ -577,7 +577,9 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 
	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));

	if (rc) {

		BNX2X_ERR("DMAE returned failure %d\n", rc);

#ifdef BNX2X_STOP_ON_ERROR

		bnx2x_panic();

#endif

	}

}
@@ -614,7 +616,9 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 
	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));

	if (rc) {

		BNX2X_ERR("DMAE returned failure %d\n", rc);

#ifdef BNX2X_STOP_ON_ERROR

		bnx2x_panic();

#endif

	}

}
@@ -9352,6 +9356,10 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global) 
	bnx2x_process_kill_chip_reset(bp, global);

	barrier();



	/* clear errors in PGB */

	if (!CHIP_IS_E1x(bp))

		REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);



	/* Recover after reset: */

	/* MCP */

	if (global && bnx2x_reset_mcp_comp(bp, val))

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -2864,6 +2864,17 @@ 
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ		 0x9430

#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE		 0x9434

#define PGLUE_B_REG_INTERNAL_VFID_ENABLE			 0x9438

/* [W 7] Writing 1 to each bit in this register clears a corresponding error

 * details register and enables logging new error details. Bit 0 - clears

 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears

 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS

 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32

 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -

 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears

 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6

 * - clears TCPL_IN_TWO_RCBS_DETAILS. */

#define PGLUE_B_REG_LATCHED_ERRORS_CLR				 0x943c



/* [R 9] Interrupt register #0 read */

#define PGLUE_B_REG_PGLUE_B_INT_STS				 0x9298

/* [RC 9] Interrupt register #0 read clear */