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Commit 9dc8a120 authored by Evan Quan's avatar Evan Quan Committed by Greg Kroah-Hartman
Browse files

drm/amd/pm: perform SMC reset on suspend/hibernation 



[ Upstream commit 277b080f98803cb73a83fb234f0be83a10e63958 ]

So that the succeeding resume can be performed based on
a clean state.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Tested-by: default avatarSandeep Raghuraman <sandy.8925@gmail.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent c1814f33

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+4 −0
Original line number Diff line number Diff line
@@ -1531,6 +1531,10 @@ int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 
	PP_ASSERT_WITH_CODE((tmp_result == 0),

			"Failed to reset to default!", result = tmp_result);



	tmp_result = smum_stop_smc(hwmgr);

	PP_ASSERT_WITH_CODE((tmp_result == 0),

			"Failed to stop smc!", result = tmp_result);



	tmp_result = smu7_force_switch_to_arbf0(hwmgr);

	PP_ASSERT_WITH_CODE((tmp_result == 0),

			"Failed to force to switch arbf0!", result = tmp_result);

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+1 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ struct pp_smumgr_func { 
	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);

	int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);

	int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */

	int (*stop_smc)(struct pp_hwmgr *hwmgr);

};



struct pp_hwmgr_func {

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+2 −0
Original line number Diff line number Diff line
@@ -113,4 +113,6 @@ extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_settin 


extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);



extern int smum_stop_smc(struct pp_hwmgr *hwmgr);



#endif

drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c

+24 −0
Original line number Diff line number Diff line
@@ -2934,6 +2934,29 @@ static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) 
	return 0;

}



static void ci_reset_smc(struct pp_hwmgr *hwmgr)

{

	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,

				  SMC_SYSCON_RESET_CNTL,

				  rst_reg, 1);

}





static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)

{

	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,

				  SMC_SYSCON_CLOCK_CNTL_0,

				  ck_disable, 1);

}



static int ci_stop_smc(struct pp_hwmgr *hwmgr)

{

	ci_reset_smc(hwmgr);

	ci_stop_smc_clock(hwmgr);



	return 0;

}



const struct pp_smumgr_func ci_smu_funcs = {

	.smu_init = ci_smu_init,

	.smu_fini = ci_smu_fini,
@@ -2957,4 +2980,5 @@ const struct pp_smumgr_func ci_smu_funcs = { 
	.is_dpm_running = ci_is_dpm_running,

	.update_dpm_settings = ci_update_dpm_settings,

	.update_smc_table = ci_update_smc_table,

	.stop_smc = ci_stop_smc,

};

drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

+8 −0
Original line number Diff line number Diff line
@@ -213,3 +213,11 @@ int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t tabl 


	return -EINVAL;

}



int smum_stop_smc(struct pp_hwmgr *hwmgr)

{

	if (hwmgr->smumgr_funcs->stop_smc)

		return hwmgr->smumgr_funcs->stop_smc(hwmgr);



	return 0;

}