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Commit 9db008d0 authored by Yijing Wang's avatar Yijing Wang Committed by Bjorn Helgaas
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staging: et131x: Use pci_dev->pcie_mpss and pcie_set_readrq() to simplify code 



The PCI core caches the "PCIe Max Payload Size Supported" in
pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword().
Also use pcie_set_readrq() instead of pcie_capability_clear_and_set_word()
to simplify code.

Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: default avatarMark Einon <mark.einon@gmail.com>
parent 03078633

drivers/staging/et131x/et131x.c

+3 −11
Original line number Diff line number Diff line
@@ -3605,17 +3605,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter, 
		goto err_out;

	}



	/* Let's set up the PORT LOGIC Register.  First we need to know what

	 * the max_payload_size is

	 */

	if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {

		dev_err(&pdev->dev,

		    "Could not read PCI config space for Max Payload Size\n");

		goto err_out;

	}

	/* Let's set up the PORT LOGIC Register. */



	/* Program the Ack/Nak latency and replay timers */

	max_payload &= 0x07;

	max_payload = pdev->pcie_mpss;



	if (max_payload < 2) {

		static const u16 acknak[2] = { 0x76, 0xD0 };
@@ -3645,8 +3638,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter, 
	}



	/* Change the max read size to 2k */

	if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,

				PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {

	if (pcie_set_readrq(pdev, 2048)) {

		dev_err(&pdev->dev,

			"Couldn't change PCI config space for Max read size\n");

		goto err_out;