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Commit 9d858bb1 authored by Borislav Petkov's avatar Borislav Petkov
Browse files

amd64_edac: fix chip select handling 



Different processor families support a different number of chip selects.
Handle this in a family-dependent way with the proper values assigned at
init time (see amd64_set_dct_base_and_mask).

Remove _DCSM_COUNT defines since they're used at one place and originate
from public documentation.

CC: Keith Mannthey <kmannth@us.ibm.com>
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent 2cff18c2

drivers/edac/amd64_edac.c

+26 −31
Original line number Original line Diff line number Diff line
@@ -189,7 +189,10 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 
/* Map from a CSROW entry to the mask entry that operates on it */

/* Map from a CSROW entry to the mask entry that operates on it */

static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)

static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)

{

{

	return csrow >> (pvt->num_dcsm >> 3);

	if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F)

		return csrow;

	else

		return csrow >> 1;

}

}





/* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */

/* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
@@ -374,7 +377,7 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) 
	 * base/mask register pair, test the condition shown near the start of

	 * base/mask register pair, test the condition shown near the start of

	 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).

	 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).

	 */

	 */

	for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {

	for (csrow = 0; csrow < pvt->cs_count; csrow++) {





		/* This DRAM chip select is disabled on this node */

		/* This DRAM chip select is disabled on this node */

		if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)

		if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
@@ -731,7 +734,7 @@ static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, 
	u64 base, mask;

	u64 base, mask;





	pvt = mci->pvt_info;

	pvt = mci->pvt_info;

	BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT));

	BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));





	base = base_from_dct_base(pvt, csrow);

	base = base_from_dct_base(pvt, csrow);

	mask = mask_from_dct_mask(pvt, csrow);

	mask = mask_from_dct_mask(pvt, csrow);
@@ -959,35 +962,27 @@ static void amd64_read_dbam_reg(struct amd64_pvt *pvt) 
 */

 */

static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)

static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)

{

{

	if (pvt->ext_model >= OPTERON_CPU_REV_F) {



	if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F) {

		pvt->dcsb_base		= REV_E_DCSB_BASE_BITS;

		pvt->dcsm_mask		= REV_E_DCSM_MASK_BITS;

		pvt->dcs_mask_notused	= REV_E_DCS_NOTUSED_BITS;

		pvt->dcs_shift		= REV_E_DCS_SHIFT;

		pvt->cs_count		= 8;

		pvt->num_dcsm		= 8;

	} else {

		pvt->dcsb_base		= REV_F_F1Xh_DCSB_BASE_BITS;

		pvt->dcsb_base		= REV_F_F1Xh_DCSB_BASE_BITS;

		pvt->dcsm_mask		= REV_F_F1Xh_DCSM_MASK_BITS;

		pvt->dcsm_mask		= REV_F_F1Xh_DCSM_MASK_BITS;

		pvt->dcs_mask_notused	= REV_F_F1Xh_DCS_NOTUSED_BITS;

		pvt->dcs_mask_notused	= REV_F_F1Xh_DCS_NOTUSED_BITS;

		pvt->dcs_shift		= REV_F_F1Xh_DCS_SHIFT;

		pvt->dcs_shift		= REV_F_F1Xh_DCS_SHIFT;





		switch (boot_cpu_data.x86) {

		if (boot_cpu_data.x86 == 0x11) {

		case 0xf:

			pvt->cs_count = 4;

			pvt->num_dcsm = REV_F_DCSM_COUNT;

			pvt->num_dcsm = 2;

			break;



		case 0x10:

			pvt->num_dcsm = F10_DCSM_COUNT;

			break;



		case 0x11:

			pvt->num_dcsm = F11_DCSM_COUNT;

			break;



		default:

			amd64_printk(KERN_ERR, "Unsupported family!\n");

			break;

		}

		} else {

		} else {

		pvt->dcsb_base		= REV_E_DCSB_BASE_BITS;

			pvt->cs_count = 8;

		pvt->dcsm_mask		= REV_E_DCSM_MASK_BITS;

			pvt->num_dcsm = 4;

		pvt->dcs_mask_notused	= REV_E_DCS_NOTUSED_BITS;

		}

		pvt->dcs_shift		= REV_E_DCS_SHIFT;

		pvt->num_dcsm		= REV_E_DCSM_COUNT;

	}

	}

}

}
@@ -1000,7 +995,7 @@ static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) 




	amd64_set_dct_base_and_mask(pvt);

	amd64_set_dct_base_and_mask(pvt);





	for (cs = 0; cs < CHIPSELECT_COUNT; cs++) {

	for (cs = 0; cs < pvt->cs_count; cs++) {

		reg = K8_DCSB0 + (cs * 4);

		reg = K8_DCSB0 + (cs * 4);

		err = pci_read_config_dword(pvt->dram_f2_ctl, reg,

		err = pci_read_config_dword(pvt->dram_f2_ctl, reg,

						&pvt->dcsb0[cs]);

						&pvt->dcsb0[cs]);
@@ -1563,7 +1558,7 @@ static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) 




	debugf1("InputAddr=0x%x  channelselect=%d\n", in_addr, cs);

	debugf1("InputAddr=0x%x  channelselect=%d\n", in_addr, cs);





	for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {

	for (csrow = 0; csrow < pvt->cs_count; csrow++) {





		cs_base = amd64_get_dct_base(pvt, cs, csrow);

		cs_base = amd64_get_dct_base(pvt, cs, csrow);

		if (!(cs_base & K8_DCSB_CS_ENABLE))

		if (!(cs_base & K8_DCSB_CS_ENABLE))
@@ -2494,7 +2489,7 @@ static void amd64_read_mc_registers(struct amd64_pvt *pvt) 
 * NOTE: CPU Revision Dependent code

 * NOTE: CPU Revision Dependent code

 *

 *

 * Input:

 * Input:

 *	@csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1)

 *	@csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)

 *	k8 private pointer to -->

 *	k8 private pointer to -->

 *			DRAM Bank Address mapping register

 *			DRAM Bank Address mapping register

 *			node_id

 *			node_id
@@ -2574,7 +2569,7 @@ static int amd64_init_csrows(struct mem_ctl_info *mci) 
		(pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"

		(pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"

		);

		);





	for (i = 0; i < CHIPSELECT_COUNT; i++) {

	for (i = 0; i < pvt->cs_count; i++) {

		csrow = &mci->csrows[i];

		csrow = &mci->csrows[i];





		if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {

		if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
@@ -2985,7 +2980,7 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt) 
		goto err_exit;

		goto err_exit;





	ret = -ENOMEM;

	ret = -ENOMEM;

	mci = edac_mc_alloc(0, CHIPSELECT_COUNT, pvt->channel_count, node_id);

	mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);

	if (!mci)

	if (!mci)

		goto err_exit;

		goto err_exit;

drivers/edac/amd64_edac.h

+6 −9
Original line number Original line Diff line number Diff line
@@ -144,7 +144,7 @@ 
#define OPTERON_CPU_REV_FA		5

#define OPTERON_CPU_REV_FA		5





/* Hardware limit on ChipSelect rows per MC and processors per system */

/* Hardware limit on ChipSelect rows per MC and processors per system */

#define CHIPSELECT_COUNT		8

#define MAX_CS_COUNT			8

#define DRAM_REG_COUNT			8

#define DRAM_REG_COUNT			8
@@ -195,7 +195,6 @@ 
 */

 */

#define REV_E_DCSB_BASE_BITS		(0xFFE0FE00ULL)

#define REV_E_DCSB_BASE_BITS		(0xFFE0FE00ULL)

#define REV_E_DCS_SHIFT			4

#define REV_E_DCS_SHIFT			4

#define REV_E_DCSM_COUNT		8





#define REV_F_F1Xh_DCSB_BASE_BITS	(0x1FF83FE0ULL)

#define REV_F_F1Xh_DCSB_BASE_BITS	(0x1FF83FE0ULL)

#define REV_F_F1Xh_DCS_SHIFT		8

#define REV_F_F1Xh_DCS_SHIFT		8
@@ -206,9 +205,6 @@ 
 */

 */

#define REV_F_DCSB_BASE_BITS		(0x1FF83FE0ULL)

#define REV_F_DCSB_BASE_BITS		(0x1FF83FE0ULL)

#define REV_F_DCS_SHIFT			8

#define REV_F_DCS_SHIFT			8

#define REV_F_DCSM_COUNT		4

#define F10_DCSM_COUNT			4

#define F11_DCSM_COUNT			2





/* DRAM CS Mask Registers */

/* DRAM CS Mask Registers */

#define K8_DCSM0			0x60

#define K8_DCSM0			0x60
@@ -447,12 +443,12 @@ struct amd64_pvt { 
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */





	/* DRAM CS Base Address Registers F2x[1,0][5C:40] */

	/* DRAM CS Base Address Registers F2x[1,0][5C:40] */

	u32 dcsb0[CHIPSELECT_COUNT];

	u32 dcsb0[MAX_CS_COUNT];

	u32 dcsb1[CHIPSELECT_COUNT];

	u32 dcsb1[MAX_CS_COUNT];





	/* DRAM CS Mask Registers F2x[1,0][6C:60] */

	/* DRAM CS Mask Registers F2x[1,0][6C:60] */

	u32 dcsm0[CHIPSELECT_COUNT];

	u32 dcsm0[MAX_CS_COUNT];

	u32 dcsm1[CHIPSELECT_COUNT];

	u32 dcsm1[MAX_CS_COUNT];





	/*

	/*

	 * Decoded parts of DRAM BASE and LIMIT Registers

	 * Decoded parts of DRAM BASE and LIMIT Registers
@@ -472,6 +468,7 @@ struct amd64_pvt { 
	 */

	 */

	u32 dcsb_base;		/* DCSB base bits */

	u32 dcsb_base;		/* DCSB base bits */

	u32 dcsm_mask;		/* DCSM mask bits */

	u32 dcsm_mask;		/* DCSM mask bits */

	u32 cs_count;		/* num chip selects (== num DCSB registers) */

	u32 num_dcsm;		/* Number of DCSM registers */

	u32 num_dcsm;		/* Number of DCSM registers */

	u32 dcs_mask_notused;	/* DCSM notused mask bits */

	u32 dcs_mask_notused;	/* DCSM notused mask bits */

	u32 dcs_shift;		/* DCSB and DCSM shift value */

	u32 dcs_shift;		/* DCSB and DCSM shift value */