Merge "disp: msm: dsi: Update pll delay calculation as per latest DSI HPG" (9d63abff) · Commits · e / devices / android_kernel_fairphone_FP4

msm/dsi/dsi_clk.h

+5 −5

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DSI_CLK_H_
		@@ -105,10 +105,10 @@ struct dsi_link_lp_clk_info {

		/**
		* struct link_clk_freq - Clock frequency information for Link clocks
		* @byte_clk_rate: Frequency of DSI byte_clk in KHz.
		* @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in KHz.
		* @pixel_clk_rate: Frequency of DSI pixel_clk in KHz.
		* @esc_clk_rate: Frequency of DSI escape clock in KHz.
		* @byte_clk_rate: Frequency of DSI byte_clk in Hz.
		* @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in Hz.
		* @pixel_clk_rate: Frequency of DSI pixel_clk in Hz.
		* @esc_clk_rate: Frequency of DSI escape clock in Hz.
		*/
		struct link_clk_freq {
		u32 byte_clk_rate;

+1 −1

Original line number	Diff line number	Diff line
		@@ -567,7 +567,7 @@ struct dsi_cmd_engine_cfg {
		* @common_config: Host configuration common to both Video and Cmd mode.
		* @video_engine: Video engine configuration if panel is in video mode.
		* @cmd_engine: Cmd engine configuration if panel is in cmd mode.
		* @esc_clk_rate_khz: Esc clock frequency in Hz.
		* @esc_clk_rate_hz: Esc clock frequency in Hz.
		* @bit_clk_rate_hz: Bit clock frequency in Hz.
		* @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs.
		* @video_timing: Video timing information of a frame.

+16 −6

Original line number	Diff line number	Diff line
		@@ -4093,18 +4093,19 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
		struct dsi_display_ctrl *m_ctrl;
		struct dsi_ctrl *dsi_ctrl;
		struct dsi_phy_cfg *cfg;
		int phy_ver;

		m_ctrl = &display->ctrl[display->clk_master_idx];
		dsi_ctrl = m_ctrl->ctrl;

		cfg = &(m_ctrl->phy->cfg);

		esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000;
		pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) /
		esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
		pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
		esc_clk_rate_hz);
		byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) /
		byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
		esc_clk_rate_hz);
		hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) /
		hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
		esc_clk_rate_hz);

		hsync_period = DSI_H_TOTAL_DSC(&mode->timing);
		@@ -4130,8 +4131,17 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
		((cfg->timing.lane_v3[4] >> 1) + 1)) /
		hr_bit_to_esc_ratio);

		/* 130 us pll delay recommended by h/w doc */
		delay->pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2;
		/*
		* 100us pll delay recommended for phy ver 2.0 and 3.0
		* 25us pll delay recommended for phy ver 4.0
		*/
		phy_ver = dsi_phy_get_version(m_ctrl->phy);
		if (phy_ver <= DSI_PHY_VERSION_3_0)
		delay->pll_delay = 100;
		else
		delay->pll_delay = 25;

		delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
		}

		/*