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Commit 9d4a2925 authored by Michael Ellerman's avatar Michael Ellerman Committed by Benjamin Herrenschmidt
Browse files

powerpc: Add MSR_64BIT 



The MSR bit which indicates 64-bit-ness is different between server and
booke, so add a #define which gives you the right mask regardless.

Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 0407a314

arch/powerpc/include/asm/reg.h

+8 −2
Original line number Diff line number Diff line
@@ -99,17 +99,23 @@ 
#define MSR_LE		__MASK(MSR_LE_LG)	/* Little Endian */



#if defined(CONFIG_PPC_BOOK3S_64)

#define MSR_64BIT	MSR_SF



/* Server variant */

#define MSR_		MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV

#define MSR_KERNEL      MSR_ | MSR_SF

#define MSR_KERNEL	MSR_ | MSR_64BIT

#define MSR_USER32	MSR_ | MSR_PR | MSR_EE

#define MSR_USER64	MSR_USER32 | MSR_SF

#define MSR_USER64	MSR_USER32 | MSR_64BIT

#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)

/* Default MSR for kernel mode. */

#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR)

#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)

#endif



#ifndef MSR_64BIT

#define MSR_64BIT	0

#endif



/* Floating Point Status and Control Register (FPSCR) Fields */

#define FPSCR_FX	0x80000000	/* FPU exception summary */

#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */

arch/powerpc/include/asm/reg_booke.h

+4 −2
Original line number Diff line number Diff line
@@ -27,10 +27,12 @@ 
#define MSR_CM		(1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */



#if defined(CONFIG_PPC_BOOK3E_64)

#define MSR_64BIT	MSR_CM



#define MSR_		MSR_ME | MSR_CE

#define MSR_KERNEL      MSR_ | MSR_CM

#define MSR_KERNEL	MSR_ | MSR_64BIT

#define MSR_USER32	MSR_ | MSR_PR | MSR_EE | MSR_DE

#define MSR_USER64	MSR_USER32 | MSR_CM | MSR_DE

#define MSR_USER64	MSR_USER32 | MSR_64BIT

#elif defined (CONFIG_40x)

#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)

#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)