[FP4-306] iris pt lightup, line up the latest codes (9d3ea3ac) · Commits · e / devices / android_kernel_fairphone_FP4

techpack/display/msm/dsi/iris/dsi_iris6_lightup.c

+13 −4

Original line number	Diff line number	Diff line
		@@ -1793,8 +1793,8 @@ int iris_parse_param(struct device_node np, struct dsi_panel panel)
		pcfg->non_embedded_xfer_len[1] = 0x400;
		}

		pcfg->dsirecover_check_method = CHECK_NONE; //CHECK_WRITE_AND_READ;
		pcfg->dsirecover_check_path = PATH_DSI; //PATH_I2C;
		pcfg->dsirecover_check_method = CHECK_WRITE_AND_READ; //CHECK_WRITE_AND_READ;
		pcfg->dsirecover_check_path = PATH_I2C; //PATH_I2C;
		pcfg->pq_update_is_dsi_hs = 1;

		rc = _iris_parse_color_temp_range(lightup_node, pcfg);
		@@ -3098,8 +3098,8 @@ int iris_lightup(struct dsi_panel panel, struct dsi_panel_cmd_set on_cmds)
		_iris_send_iris_cmds(panel, 1);

		/* do not merge */
		if (pcfg->pq_update_path == PATH_DSI)
		iris_dsirecover_check(IRIS_PQUPDATE_OP);
		//if (pcfg->pq_update_path == PATH_DSI)
		// iris_dsirecover_check(IRIS_PQUPDATE_OP);
		/* do not merge end */

		if (type == IRIS_CONT_SPLASH_LK)
		@@ -3124,6 +3124,7 @@ int iris_lightup(struct dsi_panel panel, struct dsi_panel_cmd_set on_cmds)
		pcfg->valid = FULL_LIGHTUP;
		}

		iris_dma_ch1_trigger(true, 0);
		#ifdef IRIS_MIPI_TEST
		iris_read_power_mode(panel);
		#endif
		@@ -3139,7 +3140,11 @@ int iris_enable(struct dsi_panel panel, struct dsi_panel_cmd_set on_cmds)
		int lightup_opt = iris_lightup_opt_get();
		u32 regs[] = {0xf1100808, 0xf1100818, 0xf1100a00, 0xf1100034, 0xf1100204};

		//we use PATH_I2C as the first path for pq update until panel on/off
		pcfg->pq_update_path = PATH_DSI;

		__iris_cont_splash_video_path_check(pcfg);

		IRIS_LOGI("%s(), lightup opt: 0x%x", __func__, lightup_opt);

		iris_lp_enable_pre();
		@@ -3324,6 +3329,10 @@ static int _iris_cont_splash_video_lightup_thread_main(void *data)
		iris_abyp_switch_proc(pcfg->display, IRIS_ABYP_MODE, true);
		}
		__iris_cont_splash_video_path_check(pcfg);

		//we use PATH_I2C as the first path for pq update until panel on/off
		pcfg->pq_update_path = PATH_I2C;

		IRIS_LOGI("%s(%d) <<<<<<END<<<---", __func__, __LINE__);
		return 0;
		}

techpack/display/msm/dsi/iris/dsi_iris6_lightup_ocp.c

+16 −3

Original line number	Diff line number	Diff line
		@@ -706,13 +706,20 @@ static int _iris_pt_send_cmds(struct dsi_panel *panel,
		struct dsi_panel_cmd_set panel_cmds;
		struct iris_cfg *pcfg = iris_get_cfg();
		int rc = 0;
		u8 vc_id = 0;
		memset(&panel_cmds, 0x00, sizeof(panel_cmds));

		panel_cmds.cmds = ptx_cmds;
		panel_cmds.count = cmds_cnt;
		panel_cmds.state = DSI_CMD_SET_STATE_HS;

		if (pcfg->vc_ctrl.vc_enable) {
		vc_id = (panel_cmds.state == DSI_CMD_SET_STATE_LP) ?
		pcfg->vc_ctrl.to_panel_lp_vc_id :
		pcfg->vc_ctrl.to_panel_hs_vc_id;
		}
		rc = iris_dsi_send_cmds(panel, panel_cmds.cmds,
		panel_cmds.count, panel_cmds.state, pcfg->vc_ctrl.to_panel_hs_vc_id);
		panel_cmds.count, panel_cmds.state, vc_id);

		if (iris_get_cont_splash_type() == IRIS_CONT_SPLASH_LK)
		iris_print_desc_cmds(panel_cmds.cmds,
		@@ -1037,8 +1044,14 @@ static int _iris_pt_read(struct dsi_panel_cmd_set *cmdset, uint8_t path)
		rbuf[i * 4 + j] = val.p[j];
		}
		} else {
		if (offset < 4) {
		for (i = 0; i < rlen; i++)
		rbuf[i] = val.p[offset + i];
		} else {
		val.pld32 = iris_ocp_read(address, DSI_CMD_SET_STATE_HS);
		for (i = 0; i < rlen; i++)
		rbuf[i] = val.p[i];
		}
		}

		return rc;

techpack/display/msm/dsi/iris/dsi_iris6_lp.c

+16 −6

Original line number	Diff line number	Diff line
		@@ -128,7 +128,7 @@ void iris_lp_init(void)
		iris_abyp_mode = IRIS_ABYP_MODE;
		#endif

		pcfg->read_path = PATH_DSI; //PATH_I2C;
		pcfg->read_path = PATH_I2C; //PATH_I2C;

		pcfg->abyp_ctrl.pending_mode = MAX_MODE;
		mutex_init(&pcfg->abyp_ctrl.abyp_mutex);
		@@ -177,10 +177,15 @@ void iris_lp_enable_post(void)
		lp_hdr_power_type = 2; //to make hdr power type is different
		iris_ulps_set(pcfg->lp_ctrl.ulps_lp, 1);
		iris_dynamic_power_set(pcfg->lp_ctrl.dynamic_power, 1);
		if (pcfg->cont_splash_status == 0) {
		iris_pmu_hdr_set(0, 1); //set hdr power off
		_iris_dbp_init(pcfg->dpp_only_enable, 1);
		_iris_extra_dma_trigger(0);
		} else {
		iris_pmu_hdr_set(0, 0); //set hdr power off
		_iris_dbp_init(pcfg->dpp_only_enable, 0);
		_iris_extra_dma_trigger(0);
		iris_dma_ch1_trigger(true, 0);
		}
		}

		/== PMU related APIs ==/
		@@ -464,6 +469,11 @@ static void _iris_abp_ctrl_init(bool chain)
		void iris_dma_ch1_trigger(bool en, bool chain)
		{
		struct iris_update_regval regval;
		struct iris_cfg *pcfg;

		pcfg = iris_get_cfg();
		if (pcfg->cont_splash_status == 0)
		return;

		if (iris_get_abyp_mode_blocking() != IRIS_PT_MODE)
		return;
		@@ -1114,7 +1124,7 @@ void _iris_dbp_init(bool enable, bool chain)

		regval.ip = IRIS_IP_RX;
		regval.opt_id = ID_MIPI_BYPASS_CTRL_DMA;
		regval.mask = 0xa;
		regval.mask = 0x2;
		regval.value = enable ? 0x2 : 0x0;
		iris_update_bitmask_regval_nonread(&regval, false);
		iris_init_update_ipopt_t(regval.ip, regval.opt_id, regval.opt_id, 0x01);