Loading qcom/bengal-sde.dtsi +15 −15 Original line number Diff line number Diff line Loading @@ -4,9 +4,11 @@ mdss_mdp: qcom,mdss_mdp { compatible = "qcom,sde-kms"; reg = <0x5e00000 0x8f030>, <0x5eb0000 0x2008>; <0x5eb0000 0x2008>, <0x5e8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys"; "vbif_phys", "sid_phys"; clocks = <&gcc GCC_DISP_AHB_CLK>, Loading @@ -33,13 +35,8 @@ interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; #list-cells = <1>; /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; Loading Loading @@ -78,7 +75,10 @@ qcom,sde-sspp-smart-dma-priority = <2 1>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68>; qcom,sde-mixer-pair-mask = <0>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>; Loading @@ -93,7 +93,7 @@ qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2048>; qcom,sde-sspp-linewidth = <2160>; qcom,sde-mixer-blendstages = <0x4>; qcom,sde-mixer-blendstages = <0x3>; qcom,sde-highest-bank-bit = <0x1>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-swizzle = <0x7>; Loading Loading @@ -211,10 +211,10 @@ qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 700 0 0>, <1 700 0 76800>, <1 700 0 150000>, <1 700 0 300000>; <1 590 0 0>, <1 590 0 76800>, <1 590 0 150000>, <1 590 0 300000>; }; qcom,sde-limits { Loading Loading @@ -302,8 +302,8 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 700 0 0>, <1 700 0 76800>; <1 590 0 0>, <1 590 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { Loading Loading
qcom/bengal-sde.dtsi +15 −15 Original line number Diff line number Diff line Loading @@ -4,9 +4,11 @@ mdss_mdp: qcom,mdss_mdp { compatible = "qcom,sde-kms"; reg = <0x5e00000 0x8f030>, <0x5eb0000 0x2008>; <0x5eb0000 0x2008>, <0x5e8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys"; "vbif_phys", "sid_phys"; clocks = <&gcc GCC_DISP_AHB_CLK>, Loading @@ -33,13 +35,8 @@ interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; #list-cells = <1>; /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; Loading Loading @@ -78,7 +75,10 @@ qcom,sde-sspp-smart-dma-priority = <2 1>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68>; qcom,sde-mixer-pair-mask = <0>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>; Loading @@ -93,7 +93,7 @@ qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2048>; qcom,sde-sspp-linewidth = <2160>; qcom,sde-mixer-blendstages = <0x4>; qcom,sde-mixer-blendstages = <0x3>; qcom,sde-highest-bank-bit = <0x1>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-swizzle = <0x7>; Loading Loading @@ -211,10 +211,10 @@ qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 700 0 0>, <1 700 0 76800>, <1 700 0 150000>, <1 700 0 300000>; <1 590 0 0>, <1 590 0 76800>, <1 590 0 150000>, <1 590 0 300000>; }; qcom,sde-limits { Loading Loading @@ -302,8 +302,8 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 700 0 0>, <1 700 0 76800>; <1 590 0 0>, <1 590 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { Loading