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Commit 9ce99a2c authored by Naveen Yadav's avatar Naveen Yadav
Browse files

ARM: dts: msm: Update support for dummy clocks for bengal 

Update dummy clock and GDSC nodes for Bengal device.

Change-Id: I0b72101f21c67933ef53828e4df76db9a6a7a0ae
parent a340e048

qcom/bengal-gdsc.dtsi

+64 −25
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in DISPCC*/

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "regulator-fixed";

		regulator-name = "mdss_core_gdsc";

		reg = <0x5f03000 0x4>;

		status = "disabled";

	};



	/* GDSCs in GCC */

	gcc_camss_top_gdsc: qcom,gdsc@1458004 {

		compatible = "regulator-fixed";

		regulator-name = "gcc_camss_top_gdsc";

		reg = <0x1458004 0x4>;

		regulator-name = "gcc_camss_top_gdsc";

		status = "disabled";

	};



	gcc_ufs_phy_gdsc: qcom,gdsc@1445004 {

		compatible = "regulator-fixed";

		regulator-name = "gcc_ufs_phy_gdsc";

		reg = <0x1445004 0x4>;

		regulator-name = "gcc_ufs_phy_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {

		compatible = "regulator-fixed";

		regulator-name = "gcc_usb30_prim_gdsc";

		reg = <0x141a004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	gcc_vcodec0_gdsc: qcom,gdsc@1458098 {

		compatible = "regulator-fixed";

		regulator-name = "gcc_vcodec0_gdsc";

		reg = <0x1458098 0x4>;

		regulator-name = "gcc_vcodec0_gdsc";

		status = "disabled";

	};



	gcc_venus_gdsc: qcom,gdsc@145807c {

		compatible = "regulator-fixed";

		regulator-name = "gcc_venus_gdsc";

		reg = <0x145807c 0x4>;

		regulator-name = "gcc_venus_gdsc";

		status = "disabled";

	};



	/* GDSCs in GPUCC*/

	gpu_cx_gdsc: qcom,gdsc@599106c {

		compatible = "regulator-fixed";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x599106c 0x4>;

	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {

		compatible = "qcom,gdsc";

		reg = <0x147d060 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@599100c {

	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {

		compatible = "qcom,gdsc";

		reg = <0x147d07c 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {

		compatible = "qcom,gdsc";

		reg = <0x147d074 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {

		compatible = "qcom,gdsc";

		reg = <0x147d078 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "regulator-fixed";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x599100c 0x4>;

		reg = <0x5f03000 0x4>;

		regulator-name = "mdss_core_gdsc";

		proxy-supply = <&mdss_core_gdsc>;

		qcom,proxy-consumer-enable;

		status = "disabled";

	};



	/* GDSCs in GPUCC */

	gpu_gx_domain_addr: syscon@5991508 {

		compatible = "syscon";

		reg = <0x5991508 0x4>;

	};



	gpu_cx_hw_ctrl: syscon@5991540 {

		compatible = "syscon";

		reg = <0x5991540 0x4>;
@@ -68,8 +93,22 @@ 
		reg = <0x5991008 0x4>;

	};



	gpu_gx_domain_addr: syscon@5991508 {

		compatible = "syscon";

		reg = <0x5991508 0x4>;

	gpu_cx_gdsc: qcom,gdsc@599106c {

		compatible = "regulator-fixed";

		reg = <0x599106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@599100c {

		compatible = "regulator-fixed";

		reg = <0x599100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

		domain-addr = <&gpu_gx_domain_addr>;

		qcom,reset-aon-logic;

		status = "disabled";

	};

};

qcom/bengal.dtsi

+29 −11
Original line number Diff line number Diff line
@@ -586,21 +586,21 @@ 
		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc {

	gcc: qcom,gcc@1400000 {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		clock-output-names = "gcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gcc: qcom,gcc {

	dispcc: qcom,dispcc@5f00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc {

	gpucc: qcom,gpucc@5990000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;
@@ -610,37 +610,55 @@ 


#include "bengal-gdsc.dtsi"



&mdss_core_gdsc {

&gcc_camss_top_gdsc {

	status = "ok";

};



&gcc_ufs_phy_gdsc {

	status = "ok";

};



&gcc_usb30_prim_gdsc {

	status = "ok";

};



&gcc_vcodec0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_venus_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_vcodec0_gdsc {

&hlos1_vote_turing_mmu_tbu1_gdsc {

	status = "ok";

};



&gcc_usb30_prim_gdsc {

&hlos1_vote_turing_mmu_tbu0_gdsc {

	status = "ok";

};



&gcc_camss_top_gdsc {

&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {

	status = "ok";

};



&gcc_ufs_phy_gdsc {

&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};