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Commit 9cc19733 authored by Robert Bragg's avatar Robert Bragg Committed by Ville Syrjälä
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drm/i915: fix for WaDisableDopClockGating:bdw 



This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.

v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)

Signed-off-by: default avatarRobert Bragg <robert@sixbynine.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170212133252.20990-1-robert@sixbynine.org


Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent a937eaf8

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -7229,6 +7229,14 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) 
		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);



	lpt_init_clock_gating(dev_priv);



	/* WaDisableDopClockGating:bdw

	 *

	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP

	 * clock gating.

	 */

	I915_WRITE(GEN6_UCGCTL1,

		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

}



static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −1
Original line number Diff line number Diff line
@@ -812,7 +812,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine) 
	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);



	/* WaDisableDopClockGating:bdw */

	/* WaDisableDopClockGating:bdw

	 *

	 * Also see the related UCGTCL1 write in broadwell_init_clock_gating()

	 * to disable EUTC clock gating.

	 */

	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,

			  DOP_CLOCK_GATING_DISABLE);