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Commit 9cbf3d2b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-fixes-1' of... 

Merge tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

Merge Samsung fixes for 3.16 from Kukjin Kim:

- use WFI macro in platform_do_lowpower because exynos cpuhotplug
  includes a hardcoded WFI instruction and it causes compile error
  in Thumb-2 mode.
- fix GIC reg sizes for exynos4 SoCs
- remove reset timer counter value during boot and resume for mct
  to fix a big jump in printk timestamps
- fix pm code to check cortex-A9 for another exynos SoCs
- don't rely on firmware's secondary_cpu_start for mcpm

* tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

:
  ARM: EXYNOS: Don't rely on firmware's secondary_cpu_start for mcpm
  ARM: EXYNOS: fix pm code to check for cortex A9 rather than the SoC
  clocksource: exynos_mct: Don't reset the counter during boot and resume
  ARM: dts: fix reg sizes of GIC for exynos4
  ARM: EXYNOS: Use wfi macro in platform_do_lowpower

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 6d43925f 7cbcb9d4

arch/arm/boot/dts/exynos4.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ 
		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x10490000 0x1000>, <0x10480000 0x100>;

		reg = <0x10490000 0x10000>, <0x10480000 0x10000>;

	};



	combiner: interrupt-controller@10440000 {

arch/arm/mach-exynos/hotplug.c

+1 −7
Original line number Diff line number Diff line
@@ -46,13 +46,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 
		if (cpu == 1)

			exynos_cpu_power_down(cpu);



		/*

		 * here's the WFI

		 */

		asm(".word	0xe320f003\n"

		    :

		    :

		    : "memory", "cc");

		wfi();



		if (pen_release == cpu_logical_map(cpu)) {

			/*

arch/arm/mach-exynos/mcpm-exynos.c

+6 −5
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ 


#define EXYNOS5420_CPUS_PER_CLUSTER	4

#define EXYNOS5420_NR_CLUSTERS		2

#define MCPM_BOOT_ADDR_OFFSET		0x1c



/*

 * The common v7_exit_coherency_flush API could not be used because of the
@@ -343,11 +342,13 @@ static int __init exynos_mcpm_init(void) 
	pr_info("Exynos MCPM support installed\n");



	/*

	 * Future entries into the kernel can now go

	 * through the cluster entry vectors.

	 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr

	 * as part of secondary_cpu_start().  Let's redirect it to the

	 * mcpm_entry_point().

	 */

	__raw_writel(virt_to_phys(mcpm_entry_point),

			ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);

	__raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */

	__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */

	__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);



	iounmap(ns_sram_base_addr);

arch/arm/mach-exynos/pm.c

+9 −6
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ static int exynos_pm_suspend(void) 
	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);

	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);



	if (!soc_is_exynos5250())

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)

		exynos_cpu_save_register();



	return 0;
@@ -334,7 +334,7 @@ static void exynos_pm_resume(void) 
	if (exynos_pm_central_resume())

		goto early_wakeup;



	if (!soc_is_exynos5250())

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)

		exynos_cpu_restore_register();



	/* For release retention */
@@ -353,7 +353,7 @@ static void exynos_pm_resume(void) 


	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));



	if (!soc_is_exynos5250())

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)

		scu_enable(S5P_VA_SCU);



early_wakeup:
@@ -440,15 +440,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self, 
	case CPU_PM_ENTER:

		if (cpu == 0) {

			exynos_pm_central_suspend();

			if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)

				exynos_cpu_save_register();

		}

		break;



	case CPU_PM_EXIT:

		if (cpu == 0) {

			if (!soc_is_exynos5250())

			if (read_cpuid_part_number() ==

					ARM_CPU_PART_CORTEX_A9) {

				scu_enable(S5P_VA_SCU);

				exynos_cpu_restore_register();

			}

			exynos_pm_central_resume();

		}

		break;

drivers/clocksource/exynos_mct.c

+3 −6
Original line number Diff line number Diff line
@@ -153,13 +153,10 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset) 
}



/* Clocksource handling */

static void exynos4_mct_frc_start(u32 hi, u32 lo)

static void exynos4_mct_frc_start(void)

{

	u32 reg;



	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);

	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);



	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	reg |= MCT_G_TCON_START;

	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
@@ -181,7 +178,7 @@ static cycle_t exynos4_frc_read(struct clocksource *cs) 


static void exynos4_frc_resume(struct clocksource *cs)

{

	exynos4_mct_frc_start(0, 0);

	exynos4_mct_frc_start();

}



struct clocksource mct_frc = {
@@ -200,7 +197,7 @@ static u64 notrace exynos4_read_sched_clock(void) 


static void __init exynos4_clocksource_init(void)

{

	exynos4_mct_frc_start(0, 0);

	exynos4_mct_frc_start();



	if (clocksource_register_hz(&mct_frc, clk_rate))

		panic("%s: can't register clocksource\n", mct_frc.name);