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Commit 9cbc40a0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add inline crypto register details"

parents 7964f76e f35c4942

qcom/lagoon.dtsi

+4 −58
Original line number Diff line number Diff line
@@ -652,37 +652,10 @@ 
		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			<&gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_CFG 0 0>,    /* No vote */

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_CFG 1000 0>;

				 /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;
@@ -698,11 +671,11 @@ 


	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>;

		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */
@@ -3026,32 +2999,6 @@ 
		};

	};



	sdcc1_ice: sdcc1ice@7c8000 {

		compatible = "qcom,ice";

		reg = <0x7c8000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&gcc GCC_SDCC1_AHB_CLK>,

			<&gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_SDCC_1 0 0>,

				 /* No vote */

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_SDCC_1 1000 0>;

				 /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	keepalive_opp_table: keepalive-opp-table {

		compatible = "operating-points-v2";

		opp-1 {
@@ -3084,13 +3031,12 @@ 


	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg-names = "hc_mem", "cqhci_mem";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;

		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";



		interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,

				 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;