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Commit 9c79ddaa authored Mar 14, 2017 by Mintz, Yuval Committed by David S. Miller Mar 14, 2017

qed*: Add support for QL41xxx adapters



This adds the necessary infrastructure changes for initializing
and working with the new series of QL41xxx adapaters.

It also adds 2 new PCI device-IDs to qede:
  - 0x8070 for QL41xxx PFs
  - 0x8090 for VFs spawning from QL41xxx PFs

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 942c56ad

drivers/net/ethernet/qlogic/qed/qed.h

+20 −9

Original line number	Diff line number	Diff line
		@@ -219,7 +219,9 @@ enum QED_PORT_MODE {
		QED_PORT_MODE_DE_4X20G,
		QED_PORT_MODE_DE_1X40G,
		QED_PORT_MODE_DE_2X25G,
		QED_PORT_MODE_DE_1X25G
		QED_PORT_MODE_DE_1X25G,
		QED_PORT_MODE_DE_4X25G,
		QED_PORT_MODE_DE_2X10G,
		};

		enum qed_dev_cap {
		@@ -364,7 +366,8 @@ struct qed_hwfn {
		#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
		u8 rel_pf_id; /* Relative to engine*/
		u8 abs_pf_id;
		#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
		#define QED_PATH_ID(_p_hwfn) \
		(QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
		u8 port_id;
		bool b_active;

		@@ -523,9 +526,7 @@ struct qed_dev {
		u8 dp_level;
		char name[NAME_SIZE];

		u8 type;
		#define QED_DEV_TYPE_BB (0 << 0)
		#define QED_DEV_TYPE_AH BIT(0)
		enum qed_dev_type type;
		/* Translate type/revision combo into the proper conditions */
		#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
		#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
		@@ -540,6 +541,9 @@ struct qed_dev {

		u16 vendor_id;
		u16 device_id;
		#define QED_DEV_ID_MASK 0xff00
		#define QED_DEV_ID_MASK_BB 0x1600
		#define QED_DEV_ID_MASK_AH 0x8000

		u16 chip_num;
		#define CHIP_NUM_MASK 0xffff
		@@ -654,10 +658,16 @@ struct qed_dev {
		u32 rdma_max_srq_sge;
		};

		#define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
		#define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
		#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
		#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
		#define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
		: MAX_NUM_VFS_K2)
		#define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
		: MAX_NUM_L2_QUEUES_K2)
		#define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
		: MAX_NUM_PORTS_K2)
		#define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
		: MAX_SB_PER_PATH_K2)
		#define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
		: MAX_NUM_PFS_K2)

		/**
		* @brief qed_concrete_to_sw_fid - get the sw function id from
		@@ -694,6 +704,7 @@ void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,

		void qed_clean_wfq_db(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt);
		#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
		int qed_device_num_engines(struct qed_dev *cdev);

		/* Other Linux specific common definitions */
		#define DP_NAME(cdev) ((cdev)->name)

drivers/net/ethernet/qlogic/qed/qed_debug.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1557,7 +1557,7 @@ static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn,
		dev_data->mode_enable[MODE_K2] = 1;
		} else if (QED_IS_BB_B0(p_hwfn->cdev)) {
		dev_data->chip_id = CHIP_BB_B0;
		dev_data->mode_enable[MODE_BB_B0] = 1;
		dev_data->mode_enable[MODE_BB] = 1;
		} else {
		return DBG_STATUS_UNKNOWN_CHIP;
		}

drivers/net/ethernet/qlogic/qed/qed_dev.c

+148 −38

Original line number	Diff line number	Diff line
		@@ -674,11 +674,19 @@ int qed_final_cleanup(struct qed_hwfn *p_hwfn,
		return rc;
		}

		static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
		static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
		{
		int hw_mode = 0;

		hw_mode = (1 << MODE_BB_B0);
		if (QED_IS_BB_B0(p_hwfn->cdev)) {
		hw_mode \|= 1 << MODE_BB;
		} else if (QED_IS_AH(p_hwfn->cdev)) {
		hw_mode \|= 1 << MODE_K2;
		} else {
		DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
		p_hwfn->cdev->type);
		return -EINVAL;
		}

		switch (p_hwfn->cdev->num_ports_in_engines) {
		case 1:
		@@ -693,7 +701,7 @@ static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
		default:
		DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
		p_hwfn->cdev->num_ports_in_engines);
		return;
		return -EINVAL;
		}

		switch (p_hwfn->cdev->mf_mode) {
		@@ -719,6 +727,8 @@ static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
		DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE \| NETIF_MSG_IFUP),
		"Configuring function for hw_mode: 0x%08x\n",
		p_hwfn->hw_info.hw_mode);

		return 0;
		}

		/* Init run time data for all PFs on an engine. */
		@@ -754,10 +764,10 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
		struct qed_qm_info *qm_info = &p_hwfn->qm_info;
		struct qed_qm_common_rt_init_params params;
		struct qed_dev *cdev = p_hwfn->cdev;
		u8 vf_id, max_num_vfs;
		u16 num_pfs, pf_id;
		u32 concrete_fid;
		int rc = 0;
		u8 vf_id;

		qed_init_cau_rt_data(cdev);

		@@ -814,7 +824,8 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
		qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
		}

		for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
		max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
		for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
		concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
		qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
		qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
		@@ -1135,7 +1146,9 @@ int qed_hw_init(struct qed_dev *cdev,
		/* Enable DMAE in PXP */
		rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);

		qed_calc_hw_mode(p_hwfn);
		rc = qed_calc_hw_mode(p_hwfn);
		if (rc)
		return rc;

		rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
		if (rc) {
		@@ -1485,10 +1498,25 @@ static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
		static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
		{
		/* clear indirect access */
		qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
		if (QED_IS_AH(p_hwfn->cdev)) {
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
		} else {
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
		}

		/* Clean Previous errors if such exist */
		qed_wr(p_hwfn, p_hwfn->p_main_ptt,
		@@ -1610,6 +1638,7 @@ static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
		enum qed_resources res_id)
		{
		u8 num_funcs = p_hwfn->num_funcs_on_engine;
		bool b_ah = QED_IS_AH(p_hwfn->cdev);
		struct qed_sb_cnt_info sb_cnt_info;
		u32 dflt_resc_num = 0;

		@@ -1620,17 +1649,22 @@ static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
		dflt_resc_num = sb_cnt_info.sb_cnt;
		break;
		case QED_L2_QUEUE:
		dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs;
		dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2
		: MAX_NUM_L2_QUEUES_BB) / num_funcs;
		break;
		case QED_VPORT:
		dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs;
		dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2
		: MAX_NUM_VPORTS_BB) / num_funcs;
		break;
		case QED_RSS_ENG:
		dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs;
		dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2
		: ETH_RSS_ENGINE_NUM_BB) / num_funcs;
		break;
		case QED_PQ:
		/* The granularity of the PQs is 8 */
		dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs;
		dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2
		: MAX_QM_TX_QUEUES_BB) / num_funcs;
		dflt_resc_num &= ~0x7;
		break;
		case QED_RL:
		@@ -1642,7 +1676,8 @@ static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
		dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
		break;
		case QED_ILT:
		dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs;
		dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2
		: PXP_NUM_ILT_RECORDS_BB) / num_funcs;
		break;
		case QED_LL2_QUEUE:
		dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
		@@ -1653,7 +1688,10 @@ static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
		dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
		break;
		case QED_RDMA_STATS_QUEUE:
		dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs;
		dflt_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
		: RDMA_NUM_STATISTIC_COUNTERS_BB) /
		num_funcs;

		break;
		default:
		break;
		@@ -1780,6 +1818,7 @@ static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,

		static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
		{
		bool b_ah = QED_IS_AH(p_hwfn->cdev);
		u8 res_id;
		int rc;

		@@ -1790,7 +1829,8 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
		}

		/* Sanity for ILT */
		if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) {
		if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) \|\|
		(!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
		DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
		RESC_START(p_hwfn, QED_ILT),
		RESC_END(p_hwfn, QED_ILT) - 1);
		@@ -1860,9 +1900,15 @@ static int qed_hw_get_nvm_info(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
		p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
		break;
		case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
		p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
		break;
		case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
		p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
		break;
		case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
		p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
		break;
		default:
		DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
		break;
		@@ -1976,8 +2022,9 @@ static void qed_get_num_funcs(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		{
		u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
		u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
		struct qed_dev *cdev = p_hwfn->cdev;

		num_funcs = MAX_NUM_PFS_BB;
		num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;

		/* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
		* in the other bits are selected.
		@@ -1990,13 +2037,18 @@ static void qed_get_num_funcs(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);

		if (reg_function_hide & 0x1) {
		if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
		if (QED_IS_BB(cdev)) {
		if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
		num_funcs = 0;
		eng_mask = 0xaaaa;
		} else {
		num_funcs = 1;
		eng_mask = 0x5554;
		}
		} else {
		num_funcs = 1;
		eng_mask = 0xfffe;
		}

		/* Get the number of the enabled functions on the engine */
		tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
		@@ -2027,24 +2079,12 @@ static void qed_get_num_funcs(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
		}

		static int
		qed_get_hw_info(struct qed_hwfn *p_hwfn,
		struct qed_ptt *p_ptt,
		enum qed_pci_personality personality)
		static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
		struct qed_ptt *p_ptt)
		{
		u32 port_mode;
		int rc;

		/* Since all information is common, only first hwfns should do this */
		if (IS_LEAD_HWFN(p_hwfn)) {
		rc = qed_iov_hw_info(p_hwfn);
		if (rc)
		return rc;
		}

		/* Read the port mode */
		port_mode = qed_rd(p_hwfn, p_ptt,
		CNIG_REG_NW_PORT_MODE_BB_B0);
		port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);

		if (port_mode < 3) {
		p_hwfn->cdev->num_ports_in_engines = 1;
		@@ -2057,6 +2097,54 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
		/* Default num_ports_in_engines to something */
		p_hwfn->cdev->num_ports_in_engines = 1;
		}
		}

		static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
		struct qed_ptt *p_ptt)
		{
		u32 port;
		int i;

		p_hwfn->cdev->num_ports_in_engines = 0;

		for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
		port = qed_rd(p_hwfn, p_ptt,
		CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
		if (port & 1)
		p_hwfn->cdev->num_ports_in_engines++;
		}

		if (!p_hwfn->cdev->num_ports_in_engines) {
		DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");

		/* Default num_ports_in_engine to something */
		p_hwfn->cdev->num_ports_in_engines = 1;
		}
		}

		static void qed_hw_info_port_num(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		{
		if (QED_IS_BB(p_hwfn->cdev))
		qed_hw_info_port_num_bb(p_hwfn, p_ptt);
		else
		qed_hw_info_port_num_ah(p_hwfn, p_ptt);
		}

		static int
		qed_get_hw_info(struct qed_hwfn *p_hwfn,
		struct qed_ptt *p_ptt,
		enum qed_pci_personality personality)
		{
		int rc;

		/* Since all information is common, only first hwfns should do this */
		if (IS_LEAD_HWFN(p_hwfn)) {
		rc = qed_iov_hw_info(p_hwfn);
		if (rc)
		return rc;
		}

		qed_hw_info_port_num(p_hwfn, p_ptt);

		qed_hw_get_nvm_info(p_hwfn, p_ptt);

		@@ -2096,19 +2184,33 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
		static int qed_get_dev_info(struct qed_dev *cdev)
		{
		struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
		u16 device_id_mask;
		u32 tmp;

		/* Read Vendor Id / Device Id */
		pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
		pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);

		/* Determine type */
		device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
		switch (device_id_mask) {
		case QED_DEV_ID_MASK_BB:
		cdev->type = QED_DEV_TYPE_BB;
		break;
		case QED_DEV_ID_MASK_AH:
		cdev->type = QED_DEV_TYPE_AH;
		break;
		default:
		DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
		return -EBUSY;
		}

		cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
		MISCS_REG_CHIP_NUM);
		cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
		MISCS_REG_CHIP_REV);
		MASK_FIELD(CHIP_REV, cdev->chip_rev);

		cdev->type = QED_DEV_TYPE_BB;
		/* Learn number of HW-functions */
		tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
		MISCS_REG_CMT_ENABLED_FOR_PAIR);
		@@ -2128,7 +2230,10 @@ static int qed_get_dev_info(struct qed_dev *cdev)
		MASK_FIELD(CHIP_METAL, cdev->chip_metal);

		DP_INFO(cdev->hwfns,
		"Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
		"Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
		QED_IS_BB(cdev) ? "BB" : "AH",
		'A' + cdev->chip_rev,
		(int)cdev->chip_metal,
		cdev->chip_num, cdev->chip_rev,
		cdev->chip_bond_id, cdev->chip_metal);

		@@ -3364,3 +3469,8 @@ void qed_clean_wfq_db(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		memset(p_hwfn->qm_info.wfq_data, 0,
		sizeof(p_hwfn->qm_info.wfq_data) p_hwfn->qm_info.num_vports);
		}

		int qed_device_num_engines(struct qed_dev *cdev)
		{
		return QED_IS_BB(cdev) ? 2 : 1;
		}

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+49 −12

Original line number	Diff line number	Diff line
		@@ -2502,7 +2502,7 @@ struct fw_info_location {

		enum init_modes {
		MODE_RESERVED,
		MODE_BB_B0,
		MODE_BB,
		MODE_K2,
		MODE_ASIC,
		MODE_RESERVED2,
		@@ -9431,11 +9431,24 @@ struct eth_stats {
		u64 r511;
		u64 r1023;
		u64 r1518;

		union {
		struct {
		u64 r1522;
		u64 r2047;
		u64 r4095;
		u64 r9216;
		u64 r16383;
		} bb0;
		struct {
		u64 unused1;
		u64 r1519_to_max;
		u64 unused2;
		u64 unused3;
		u64 unused4;
		} ah0;
		} u0;

		u64 rfcs;
		u64 rxcf;
		u64 rxpf;
		@@ -9452,14 +9465,36 @@ struct eth_stats {
		u64 t511;
		u64 t1023;
		u64 t1518;

		union {
		struct {
		u64 t2047;
		u64 t4095;
		u64 t9216;
		u64 t16383;
		} bb1;
		struct {
		u64 t1519_to_max;
		u64 unused6;
		u64 unused7;
		u64 unused8;
		} ah1;
		} u1;

		u64 txpf;
		u64 txpp;

		union {
		struct {
		u64 tlpiec;
		u64 tncl;
		} bb2;
		struct {
		u64 unused9;
		u64 unused10;
		} ah2;
		} u2;

		u64 rbyte;
		u64 rxuca;
		u64 rxmca;
		@@ -10263,6 +10298,8 @@ struct nvm_cfg1_glob {
		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF

		u32 e_lane_cfg1;
		u32 e_lane_cfg2;
		u32 f_lane_cfg1;

drivers/net/ethernet/qlogic/qed/qed_l2.c

+109 −75

Original line number	Diff line number	Diff line
		@@ -1470,13 +1470,20 @@ static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
		memset(&pstats, 0, sizeof(pstats));
		qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);

		p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
		p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
		p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
		p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
		p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
		p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
		p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
		p_stats->common.tx_ucast_bytes +=
		HILO_64_REGPAIR(pstats.sent_ucast_bytes);
		p_stats->common.tx_mcast_bytes +=
		HILO_64_REGPAIR(pstats.sent_mcast_bytes);
		p_stats->common.tx_bcast_bytes +=
		HILO_64_REGPAIR(pstats.sent_bcast_bytes);
		p_stats->common.tx_ucast_pkts +=
		HILO_64_REGPAIR(pstats.sent_ucast_pkts);
		p_stats->common.tx_mcast_pkts +=
		HILO_64_REGPAIR(pstats.sent_mcast_pkts);
		p_stats->common.tx_bcast_pkts +=
		HILO_64_REGPAIR(pstats.sent_bcast_pkts);
		p_stats->common.tx_err_drop_pkts +=
		HILO_64_REGPAIR(pstats.error_drop_pkts);
		}

		static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
		@@ -1502,9 +1509,9 @@ static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
		memset(&tstats, 0, sizeof(tstats));
		qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);

		p_stats->mftag_filter_discards +=
		p_stats->common.mftag_filter_discards +=
		HILO_64_REGPAIR(tstats.mftag_filter_discard);
		p_stats->mac_filter_discards +=
		p_stats->common.mac_filter_discards +=
		HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
		}

		@@ -1539,12 +1546,15 @@ static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
		memset(&ustats, 0, sizeof(ustats));
		qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);

		p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
		p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
		p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
		p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
		p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
		p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
		p_stats->common.rx_ucast_bytes +=
		HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
		p_stats->common.rx_mcast_bytes +=
		HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
		p_stats->common.rx_bcast_bytes +=
		HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
		p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
		p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
		p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
		}

		static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
		@@ -1578,16 +1588,18 @@ static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
		memset(&mstats, 0, sizeof(mstats));
		qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);

		p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
		p_stats->packet_too_big_discard +=
		p_stats->common.no_buff_discards +=
		HILO_64_REGPAIR(mstats.no_buff_discard);
		p_stats->common.packet_too_big_discard +=
		HILO_64_REGPAIR(mstats.packet_too_big_discard);
		p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
		p_stats->tpa_coalesced_pkts +=
		p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
		p_stats->common.tpa_coalesced_pkts +=
		HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
		p_stats->tpa_coalesced_events +=
		p_stats->common.tpa_coalesced_events +=
		HILO_64_REGPAIR(mstats.tpa_coalesced_events);
		p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
		p_stats->tpa_coalesced_bytes +=
		p_stats->common.tpa_aborts_num +=
		HILO_64_REGPAIR(mstats.tpa_aborts_num);
		p_stats->common.tpa_coalesced_bytes +=
		HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
		}

		@@ -1595,6 +1607,7 @@ static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
		struct qed_ptt *p_ptt,
		struct qed_eth_stats *p_stats)
		{
		struct qed_eth_stats_common *p_common = &p_stats->common;
		struct port_stats port_stats;
		int j;

		@@ -1605,54 +1618,75 @@ static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
		offsetof(struct public_port, stats),
		sizeof(port_stats));

		p_stats->rx_64_byte_packets += port_stats.eth.r64;
		p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
		p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
		p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
		p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
		p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
		p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
		p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
		p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
		p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
		p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
		p_stats->rx_crc_errors += port_stats.eth.rfcs;
		p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
		p_stats->rx_pause_frames += port_stats.eth.rxpf;
		p_stats->rx_pfc_frames += port_stats.eth.rxpp;
		p_stats->rx_align_errors += port_stats.eth.raln;
		p_stats->rx_carrier_errors += port_stats.eth.rfcr;
		p_stats->rx_oversize_packets += port_stats.eth.rovr;
		p_stats->rx_jabbers += port_stats.eth.rjbr;
		p_stats->rx_undersize_packets += port_stats.eth.rund;
		p_stats->rx_fragments += port_stats.eth.rfrg;
		p_stats->tx_64_byte_packets += port_stats.eth.t64;
		p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
		p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
		p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
		p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
		p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
		p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
		p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
		p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
		p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
		p_stats->tx_pause_frames += port_stats.eth.txpf;
		p_stats->tx_pfc_frames += port_stats.eth.txpp;
		p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
		p_stats->tx_total_collisions += port_stats.eth.tncl;
		p_stats->rx_mac_bytes += port_stats.eth.rbyte;
		p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
		p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
		p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
		p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
		p_stats->tx_mac_bytes += port_stats.eth.tbyte;
		p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
		p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
		p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
		p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
		p_common->rx_64_byte_packets += port_stats.eth.r64;
		p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
		p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
		p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
		p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
		p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
		p_common->rx_crc_errors += port_stats.eth.rfcs;
		p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
		p_common->rx_pause_frames += port_stats.eth.rxpf;
		p_common->rx_pfc_frames += port_stats.eth.rxpp;
		p_common->rx_align_errors += port_stats.eth.raln;
		p_common->rx_carrier_errors += port_stats.eth.rfcr;
		p_common->rx_oversize_packets += port_stats.eth.rovr;
		p_common->rx_jabbers += port_stats.eth.rjbr;
		p_common->rx_undersize_packets += port_stats.eth.rund;
		p_common->rx_fragments += port_stats.eth.rfrg;
		p_common->tx_64_byte_packets += port_stats.eth.t64;
		p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
		p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
		p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
		p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
		p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
		p_common->tx_pause_frames += port_stats.eth.txpf;
		p_common->tx_pfc_frames += port_stats.eth.txpp;
		p_common->rx_mac_bytes += port_stats.eth.rbyte;
		p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
		p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
		p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
		p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
		p_common->tx_mac_bytes += port_stats.eth.tbyte;
		p_common->tx_mac_uc_packets += port_stats.eth.txuca;
		p_common->tx_mac_mc_packets += port_stats.eth.txmca;
		p_common->tx_mac_bc_packets += port_stats.eth.txbca;
		p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
		for (j = 0; j < 8; j++) {
		p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
		p_stats->brb_discards += port_stats.brb.brb_discard[j];
		p_common->brb_truncates += port_stats.brb.brb_truncate[j];
		p_common->brb_discards += port_stats.brb.brb_discard[j];
		}

		if (QED_IS_BB(p_hwfn->cdev)) {
		struct qed_eth_stats_bb *p_bb = &p_stats->bb;

		p_bb->rx_1519_to_1522_byte_packets +=
		port_stats.eth.u0.bb0.r1522;
		p_bb->rx_1519_to_2047_byte_packets +=
		port_stats.eth.u0.bb0.r2047;
		p_bb->rx_2048_to_4095_byte_packets +=
		port_stats.eth.u0.bb0.r4095;
		p_bb->rx_4096_to_9216_byte_packets +=
		port_stats.eth.u0.bb0.r9216;
		p_bb->rx_9217_to_16383_byte_packets +=
		port_stats.eth.u0.bb0.r16383;
		p_bb->tx_1519_to_2047_byte_packets +=
		port_stats.eth.u1.bb1.t2047;
		p_bb->tx_2048_to_4095_byte_packets +=
		port_stats.eth.u1.bb1.t4095;
		p_bb->tx_4096_to_9216_byte_packets +=
		port_stats.eth.u1.bb1.t9216;
		p_bb->tx_9217_to_16383_byte_packets +=
		port_stats.eth.u1.bb1.t16383;
		p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
		p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
		} else {
		struct qed_eth_stats_ah *p_ah = &p_stats->ah;

		p_ah->rx_1519_to_max_byte_packets +=
		port_stats.eth.u0.ah0.r1519_to_max;
		p_ah->tx_1519_to_max_byte_packets =
		port_stats.eth.u1.ah1.t1519_to_max;
		}
		}