Merge branch 'topic/stm' into for-linus

- #dma-cells : Must be <4>. See DMA client paragraph for more details.

Optional properties:

- dma-requests : Number of DMA requests supported.

- resets: Reference to a reset controller asserting the DMA controller

- st,mem2mem: boolean; if defined, it indicates that the controller supports

  memory-to-memory transfer

		#dma-cells = <4>;

		st,mem2mem;

		resets = <&rcc 150>;

		dma-requests = <8>;

	};

* DMA client

DMA clients connected to the STM32 DMA controller must use the format

described in the dma.txt file, using a five-cell specifier for each

described in the dma.txt file, using a four-cell specifier for each

channel: a phandle to the DMA controller plus the following four integer cells:

1. The channel id

STM32 DMA MUX (DMA request router)

Required properties:

- compatible:	"st,stm32h7-dmamux"

- reg:		Memory map for accessing module

- #dma-cells:	Should be set to <3>.

		First parameter is request line number.

		Second is DMA channel configuration

		Third is Fifo threshold

		For more details about the three cells, please see

		stm32-dma.txt documentation binding file

- dma-masters:	Phandle pointing to the DMA controllers.

		Several controllers are allowed. Only "st,stm32-dma" DMA

		compatible are supported.

Optional properties:

- dma-channels : Number of DMA requests supported.

- dma-requests : Number of DMAMUX requests supported.

- resets: Reference to a reset controller asserting the DMA controller

- clocks: Input clock of the DMAMUX instance.

Example:

/* DMA controller 1 */

dma1: dma-controller@40020000 {

	compatible = "st,stm32-dma";

	reg = <0x40020000 0x400>;

	interrupts = <11>,

		     <12>,

		     <13>,

		     <14>,

		     <15>,

		     <16>,

		     <17>,

		     <47>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};

/* DMA controller 1 */

dma2: dma@40020400 {

	compatible = "st,stm32-dma";

	reg = <0x40020400 0x400>;

	interrupts = <56>,

		     <57>,

		     <58>,

		     <59>,

		     <60>,

		     <68>,

		     <69>,

		     <70>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};

/* DMA mux */

dmamux1: dma-router@40020800 {

	compatible = "st,stm32h7-dmamux";

	reg = <0x40020800 0x3c>;

	#dma-cells = <3>;

	dma-requests = <128>;

	dma-channels = <16>;

	dma-masters = <&dma1 &dma2>;

	clocks = <&timer_clk>;

};

/* DMA client */

usart1: serial@40011000 {

	compatible = "st,stm32-usart", "st,stm32-uart";

	reg = <0x40011000 0x400>;

	interrupts = <37>;

	clocks = <&timer_clk>;

	dmas = <&dmamux1 41 0x414 0>,

	       <&dmamux1 42 0x414 0>;

	dma-names = "rx", "tx";

};

* STMicroelectronics STM32 MDMA controller

The STM32 MDMA is a general-purpose direct memory access controller capable of

supporting 64 independent DMA channels with 256 HW requests.

Required properties:

- compatible: Should be "st,stm32h7-mdma"

- reg: Should contain MDMA registers location and length. This should include

  all of the per-channel registers.

- interrupts: Should contain the MDMA interrupt.

- clocks: Should contain the input clock of the DMA instance.

- resets: Reference to a reset controller asserting the DMA controller.

- #dma-cells : Must be <5>. See DMA client paragraph for more details.

Optional properties:

- dma-channels: Number of DMA channels supported by the controller.

- dma-requests: Number of DMA request signals supported by the controller.

- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via

  AHB bus.

Example:

	mdma1: dma@52000000 {

		compatible = "st,stm32h7-mdma";

		reg = <0x52000000 0x1000>;

		interrupts = <122>;

		clocks = <&timer_clk>;

		resets = <&rcc 992>;

		#dma-cells = <5>;

		dma-channels = <16>;

		dma-requests = <32>;

		st,ahb-addr-masks = <0x20000000>, <0x00000000>;

	};

* DMA client

DMA clients connected to the STM32 MDMA controller must use the format

described in the dma.txt file, using a five-cell specifier for each channel:

a phandle to the MDMA controller plus the following five integer cells:

1. The request line number

2. The priority level

	0x00: Low

	0x01: Medium

	0x10: High

	0x11: Very high

3. A 32bit mask specifying the DMA channel configuration

 -bit 0-1: Source increment mode

	0x00: Source address pointer is fixed

	0x10: Source address pointer is incremented after each data transfer

	0x11: Source address pointer is decremented after each data transfer

 -bit 2-3: Destination increment mode

	0x00: Destination address pointer is fixed

	0x10: Destination address pointer is incremented after each data

	transfer

	0x11: Destination address pointer is decremented after each data

	transfer

 -bit 8-9: Source increment offset size

	0x00: byte (8bit)

	0x01: half-word (16bit)

	0x10: word (32bit)

	0x11: double-word (64bit)

 -bit 10-11: Destination increment offset size

	0x00: byte (8bit)

	0x01: half-word (16bit)

	0x10: word (32bit)

	0x11: double-word (64bit)

-bit 25-18: The number of bytes to be transferred in a single transfer

	(min = 1 byte, max = 128 bytes)

-bit 29:28: Trigger Mode

	0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)

	0x01: Each MDMA request triggers a block transfer (max 64K bytes)

	0x10: Each MDMA request triggers a repeated block transfer

	0x11: Each MDMA request triggers a linked list transfer

4. A 32bit value specifying the register to be used to acknowledge the request

   if no HW ack signal is used by the MDMA client

5. A 32bit mask specifying the value to be written to acknowledge the request

   if no HW ack signal is used by the MDMA client

Example:

	i2c4: i2c@5c002000 {

		compatible = "st,stm32f7-i2c";

		reg = <0x5c002000 0x400>;

		interrupts = <95>,

			     <96>;

		clocks = <&timer_clk>;

		#address-cells = <1>;

		#size-cells = <0>;

		dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>,

		       <&mdma1 37 0x0 0x40002 0x0 0x0>;

		dma-names = "rx", "tx";

		status = "disabled";

	};

	  If you have a board based on such a MCU and wish to use DMA say Y

	  here.

config STM32_DMAMUX

	bool "STMicroelectronics STM32 dma multiplexer support"

	depends on STM32_DMA || COMPILE_TEST

	help

	  Enable support for the on-chip DMA multiplexer on STMicroelectronics

	  STM32 MCUs.

	  If you have a board based on such a MCU and wish to use DMAMUX say Y

	  here.

config STM32_MDMA

	bool "STMicroelectronics STM32 master dma support"

	depends on ARCH_STM32 || COMPILE_TEST

	depends on OF

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	help

	  Enable support for the on-chip MDMA controller on STMicroelectronics

	  STM32 platforms.

	  If you have a board based on STM32 SoC and wish to use the master DMA

	  say Y here.

config S3C24XX_DMAC

	bool "Samsung S3C24XX DMA support"

	depends on ARCH_S3C24XX || COMPILE_TEST

obj-$(CONFIG_SIRF_DMA) += sirf-dma.o

obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o

obj-$(CONFIG_STM32_DMA) += stm32-dma.o

obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o

obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o

obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o

obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o

obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o