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Commit 9c345b42 authored by Jayaprakash's avatar Jayaprakash Committed by Ritesh Kumar
Browse files

ARM: dts: msm: add display DT node for lito target 

Add all display related DT nodes for lito target.

Change-Id: Ifa077076761c2ec5ff63788cbcb02e3b8d50b8b6
parent aef03761

qcom/lito-cdp.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#include "lito-audio-overlay.dtsi"

#include "lito-pmic-overlay.dtsi"

#include "lito-camera-sensor-cdp.dtsi"

#include "lito-sde-display.dtsi"



&soc {
@@ -263,3 +264,37 @@ 
		st,regulator_avdd = "avdd";

	};

};



&dsi_sw43404_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&dsi_sw43404_amoled_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&dsi_sw43404_amoled_fhd_plus_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;

};

qcom/lito-mtp.dtsi

+35 −1
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#include "lito-audio-overlay.dtsi"

#include "lito-pmic-overlay.dtsi"

#include "lito-camera-sensor-mtp.dtsi"

#include "lito-sde-display.dtsi"



&soc {
@@ -182,7 +183,6 @@ 
&qupv3_se7_i2c {

	#address-cells = <1>;

	#size-cells = <0>;



	status = "ok";



	st_fts@49 {
@@ -203,3 +203,37 @@ 
		st,y-flip = <1>;

	};

};



&dsi_sw43404_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&dsi_sw43404_amoled_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&dsi_sw43404_amoled_fhd_plus_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 10 0>;

	qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;

};

qcom/lito-pinctrl.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -1475,5 +1475,59 @@ 
				};

			};

		};



		pmx_sde_te {

			sde_te_active: sde_te_active {

				mux {

					pins = "gpio10";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio10";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			sde_te_suspend: sde_te_suspend {

				mux {

					pins = "gpio10";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio10";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			sde_te1_active: sde_te1_active {

				mux {

					pins = "gpio11";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio11";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			sde_te1_suspend: sde_te1_suspend {

				mux {

					pins = "gpio11";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio11";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};

		};

	};

};

qcom/lito-sde-display.dtsi

0 → 100644
+176 −0
Original line number Diff line number Diff line 
#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"

#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"

#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"

#include <dt-bindings/clock/mdss-7nm-pll-clk.h>



&pm8150l_gpios {

	disp_pins {

		disp_pins_default: disp_pins_default {

			pins = "gpio3";

			function = "func1";

			qcom,drive-strength = <2>;

			power-source = <1>;

			bias-disable;

			output-low;

		};

	};

};



&soc {

	ext_disp: qcom,msm-ext-disp {

		compatible = "qcom,msm-ext-disp";



		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

	};



	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "vdd";

			qcom,supply-min-voltage = <3000000>;

			qcom,supply-max-voltage = <3000000>;

			qcom,supply-enable-load = <857000>;

			qcom,supply-disable-load = <0>;

			qcom,supply-post-on-sleep = <0>;

		};

	};



	dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "avdd";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

		};

	};



	sde_dsi: qcom,dsi-display-primary {

		compatible = "qcom,dsi-display";

		label = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;



		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te_active &disp_pins_default>;

		pinctrl-1 = <&sde_te_suspend>;



		qcom,platform-te-gpio = <&tlmm 10 0>;

		qcom,panel-te-source = <0>;



		vddio-supply = <&L1C>;

		vdd-supply = <&L16A>;



		qcom,mdp = <&mdss_mdp>;

		qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;

	};



	sde_dsi1: qcom,dsi-display-secondary {

		status = "disabled";

		compatible = "qcom,dsi-display";

		label = "secondary";



		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;

		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;



		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te1_active>;

		pinctrl-1 = <&sde_te1_suspend>;



		qcom,platform-te-gpio = <&tlmm 11 0>;

		qcom,panel-te-source = <1>;



		vddio-supply = <&L1C>;

		vdd-supply = <&L16A>;



		qcom,mdp = <&mdss_mdp>;

	};



	sde_wb: qcom,wb-display@0 {

		compatible = "qcom,wb-display";

		cell-index = <0>;

		label = "wb_display";

	};

};



&mdss_mdp {

	connectors = <&sde_wb &sde_dsi>;

};



/* PHY TIMINGS REVISION W */

&dsi_sw43404_amoled_cmd {

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05

				05 03 02 04 00 12 15];

			qcom,display-topology = <2 2 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sw43404_amoled_video {

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05

				05 03 02 04 00 12 15];

			qcom,display-topology = <2 2 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sw43404_amoled_fhd_plus_cmd {

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04

				05 02 03 04 00 11 14];

			qcom,display-topology = <2 2 1>;

			qcom,default-topology-index = <0>;

		};

	};

};

qcom/lito-sde-pll.dtsi

0 → 100644
+59 −0
Original line number Diff line number Diff line 
&soc {

	mdss_dsi0_pll: qcom,mdss_dsi0_pll {

		compatible = "qcom,mdss_dsi_pll_7nm_v4_1";

		label = "MDSS DSI 0 PLL";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0xae94900 0x280>,

		      <0xae94400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi1_pll: qcom,mdss_dsi1_pll {

		compatible = "qcom,mdss_dsi_pll_7nm_v4_1";

		label = "MDSS DSI 1 PLL";

		cell-index = <1>;

		#clock-cells = <1>;

		reg = <0xae96900 0x280>,

		      <0xae96400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};

};