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Commit 9bfe9f08 authored by Tao,Zhang's avatar Tao,Zhang
Browse files

ARM: dts: msm: Add CTI config for ETB and ETR for lito 

Add CTI flush and reset config to coresight device tree for ETR
and ETB for lito.

Change-Id: Ic4596f950dfdf3d8823ade3f7369b9b207b7a532
parent 31aaa3dc

qcom/lito-coresight.dtsi

+2 −1
Original line number Original line Diff line number Diff line
@@ -104,6 +104,7 @@ 
		reg-names = "tmc-base";

		reg-names = "tmc-base";





		coresight-name = "coresight-tmc-etf";

		coresight-name = "coresight-tmc-etf";

		coresight-ctis = <&cti0_swao &cti3_swao>;

		coresight-csr = <&swao_csr>;

		coresight-csr = <&swao_csr>;

		clocks = <&aopcc QDSS_CLK>;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "apb_pclk";

		clock-names = "apb_pclk";
@@ -300,7 +301,7 @@ 




		qcom,sw-usb;

		qcom,sw-usb;

		coresight-name = "coresight-tmc-etr";

		coresight-name = "coresight-tmc-etr";

		coresight-ctis = <&cti0 &cti0>;

		coresight-ctis = <&cti0 &cti3_swao>;

		coresight-csr = <&csr>;

		coresight-csr = <&csr>;





		clocks = <&aopcc QDSS_CLK>;

		clocks = <&aopcc QDSS_CLK>;