Merge "ARM: dts: msm: Add I3C device node for QUPV3 SE for lito" (9bbd91f2) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/lito-pinctrl.dtsi

+56 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,62 @@
		};
		};

		qupv3_se0_i3c_pins: qupv3_se0_i3c_pins {
		qupv3_se0_i3c_active: qupv3_se0_i3c_active {
		mux {
		pins = "gpio42", "gpio43";
		function = "ibi_i3c";
		};

		config {
		pins = "gpio42", "gpio43";
		drive-strength = <16>;
		bias-pull-up;
		};
		};

		qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep {
		mux {
		pins = "gpio42", "gpio43";
		function = "gpio";
		};

		config {
		pins = "gpio42", "gpio43";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se6_i3c_pins: qupv3_se6_i3c_pins {
		qupv3_se6_i3c_active: qupv3_se6_i3c_active {
		mux {
		pins = "gpio59", "gpio60";
		function = "ibi_i3c";
		};

		config {
		pins = "gpio59", "gpio60";
		drive-strength = <16>;
		bias-pull-up;
		};
		};

		qupv3_se6_i3c_sleep: qupv3_se6_i3c_sleep {
		mux {
		pins = "gpio59", "gpio60";
		function = "gpio";
		};

		config {
		pins = "gpio59", "gpio60";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		ufs_dev_reset_assert: ufs_dev_reset_assert {
		config {
		pins = "ufs_reset";

+38 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,25 @@
		status = "disabled";
		};

		/* QUPV3_0_SE0 */
		i3c0: i3c-master@880000 {
		compatible = "qcom,geni-i3c";
		reg = <0x880000 0x4000>,
		<0xec30000 0x10000>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i3c_active>;
		pinctrl-1 = <&qupv3_se0_i3c_sleep>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <3>;
		#size-cells = <0>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/QUPv3_1 /
		qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		@@ -77,4 +96,23 @@
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* QUPV3_1_SE0 */
		i3c1: i3c-master@980000 {
		compatible = "qcom,geni-i3c";
		reg = <0x980000 0x4000>,
		<0xec40000 0x10000>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i3c_active>;
		pinctrl-1 = <&qupv3_se6_i3c_sleep>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <3>;
		#size-cells = <0>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};
		};