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Commit 9bb59b96 authored by Hariprasad Shenai's avatar Hariprasad Shenai Committed by David S. Miller
Browse files

cxgb4: Fix T5 adapter accessing T4 adapter registers 



Fixes few register access for both T4 and T5.
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2
is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use
MPS_T5_TRC_RSS_CONTROL.

Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 63a92fe6

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+3 −1
Original line number Diff line number Diff line
@@ -1253,7 +1253,9 @@ freeout: t4_free_sge_resources(adap); 
			goto freeout;

	}



	t4_write_reg(adap, MPS_TRC_RSS_CONTROL,

	t4_write_reg(adap, is_t4(adap->params.chip) ?

				MPS_TRC_RSS_CONTROL :

				MPS_T5_TRC_RSS_CONTROL,

		     RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |

		     QUEUENUMBER(s->ethrxq[0].rspq.abs_id));

	return 0;

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+19 −10
Original line number Diff line number Diff line
@@ -1403,6 +1403,7 @@ static void pcie_intr_handler(struct adapter *adapter) 


	int fat;



	if (is_t4(adapter->params.chip))

		fat = t4_handle_intr_status(adapter,

					    PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,

					    sysbus_intr_info) +
@@ -1410,8 +1411,10 @@ static void pcie_intr_handler(struct adapter *adapter) 
					      PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,

					      pcie_port_intr_info) +

			t4_handle_intr_status(adapter, PCIE_INT_CAUSE,

				    is_t4(adapter->params.chip) ?

				    pcie_intr_info : t5_pcie_intr_info);

					      pcie_intr_info);

	else

		fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,

					    t5_pcie_intr_info);



	if (fat)

		t4_fatal_err(adapter);
@@ -1777,10 +1780,16 @@ static void ma_intr_handler(struct adapter *adap) 
{

	u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);



	if (status & MEM_PERR_INT_CAUSE)

	if (status & MEM_PERR_INT_CAUSE) {

		dev_alert(adap->pdev_dev,

			  "MA parity error, parity status %#x\n",

			  t4_read_reg(adap, MA_PARITY_ERROR_STATUS));

		if (is_t5(adap->params.chip))

			dev_alert(adap->pdev_dev,

				  "MA parity error, parity status %#x\n",

				  t4_read_reg(adap,

					      MA_PARITY_ERROR_STATUS2));

	}

	if (status & MEM_WRAP_INT_CAUSE) {

		v = t4_read_reg(adap, MA_INT_WRAP_STATUS);

		dev_alert(adap->pdev_dev, "MA address wrap-around error by "

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -511,6 +511,7 @@ 
#define  MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)

#define MA_PCIE_FW 0x30b8

#define MA_PARITY_ERROR_STATUS 0x77f4

#define MA_PARITY_ERROR_STATUS2 0x7804



#define MA_EXT_MEMORY1_BAR 0x7808

#define EDC_0_BASE_ADDR 0x7900
@@ -959,6 +960,7 @@ 
#define  TRCMULTIFILTER     0x00000001U



#define MPS_TRC_RSS_CONTROL 0x9808

#define MPS_T5_TRC_RSS_CONTROL 0xa00c

#define  RSSCONTROL_MASK    0x00ff0000U

#define  RSSCONTROL_SHIFT   16

#define  RSSCONTROL(x)      ((x) << RSSCONTROL_SHIFT)