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Commit 9b8777e3 authored by John Crispin's avatar John Crispin Committed by Greg Kroah-Hartman
Browse files

serial: of: add a PORT_RT2880 definition 



The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7af0ea5d

drivers/tty/serial/8250/8250_core.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -2640,8 +2640,11 @@ serial8250_pm(struct uart_port *port, unsigned int state, 




static unsigned int serial8250_port_size(struct uart_8250_port *pt)

static unsigned int serial8250_port_size(struct uart_8250_port *pt)

{

{

	if (pt->port.iotype == UPIO_AU)

	if (pt->port.iotype == UPIO_AU) {

		if (pt->port.type == PORT_RT2880)

			return 0x100;

		return 0x1000;

		return 0x1000;

	}

	if (is_omap1_8250(pt))

	if (is_omap1_8250(pt))

		return 0x16 << pt->port.regshift;

		return 0x16 << pt->port.regshift;

drivers/tty/serial/of_serial.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -130,8 +130,15 @@ static int of_platform_serial_setup(struct platform_device *ofdev, 




	port->dev = &ofdev->dev;

	port->dev = &ofdev->dev;





	if (type == PORT_TEGRA)

	switch (type) {

	case PORT_TEGRA:

		port->handle_break = tegra_serial_handle_break;

		port->handle_break = tegra_serial_handle_break;

		break;



	case PORT_RT2880:

		port->iotype = UPIO_AU;

		break;

	}





	return 0;

	return 0;

out:

out:
@@ -317,6 +324,7 @@ static struct of_device_id of_platform_serial_table[] = { 
	{ .compatible = "ns16850",  .data = (void *)PORT_16850, },

	{ .compatible = "ns16850",  .data = (void *)PORT_16850, },

	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },

	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },

	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },

	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },

	{ .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },

	{ .compatible = "altr,16550-FIFO32",

	{ .compatible = "altr,16550-FIFO32",

		.data = (void *)PORT_ALTR_16550_F32, },

		.data = (void *)PORT_ALTR_16550_F32, },

	{ .compatible = "altr,16550-FIFO64",

	{ .compatible = "altr,16550-FIFO64",

include/uapi/linux/serial_core.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -54,7 +54,8 @@ 
#define PORT_ALTR_16550_F32 26	/* Altera 16550 UART with 32 FIFOs */

#define PORT_ALTR_16550_F32 26	/* Altera 16550 UART with 32 FIFOs */

#define PORT_ALTR_16550_F64 27	/* Altera 16550 UART with 64 FIFOs */

#define PORT_ALTR_16550_F64 27	/* Altera 16550 UART with 64 FIFOs */

#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */

#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */

#define PORT_MAX_8250	28	/* max port ID */

#define PORT_RT2880	29	/* Ralink RT2880 internal UART */

#define PORT_MAX_8250	29	/* max port ID */





/*

/*

 * ARM specific type numbers.  These are not currently guaranteed

 * ARM specific type numbers.  These are not currently guaranteed