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Commit 9b56febe authored by Russell King's avatar Russell King
Browse files

ARM: entry: move IRQ tracing exit into svc_exit 



The IRQ tracing exit path is much the same between all SVC mode
exits, so move this into the svc_exit macro.  Use a macro parameter
to identify the IRQ case, which is the only different case there is.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 651e9499

arch/arm/kernel/entry-armv.S

+1 −26
Original line number Original line Diff line number Diff line
@@ -197,13 +197,6 @@ __dabt_svc: 
	@ IRQs off again before pulling preserved data off the stack

	@ IRQs off again before pulling preserved data off the stack

	@

	@

	disable_irq_notrace

	disable_irq_notrace



#ifdef CONFIG_TRACE_IRQFLAGS

	tst	r5, #PSR_I_BIT

	bleq	trace_hardirqs_on

	tst	r5, #PSR_I_BIT

	blne	trace_hardirqs_off

#endif

	svc_exit r5				@ return from exception

	svc_exit r5				@ return from exception

 UNWIND(.fnend		)

 UNWIND(.fnend		)

ENDPROC(__dabt_svc)

ENDPROC(__dabt_svc)
@@ -223,12 +216,7 @@ __irq_svc: 
	blne	svc_preempt

	blne	svc_preempt

#endif

#endif





#ifdef CONFIG_TRACE_IRQFLAGS

	svc_exit r5, irq = 1			@ return from exception

	@ The parent context IRQs must have been enabled to get here in

	@ the first place, so there's no point checking the PSR I bit.

	bl	trace_hardirqs_on

#endif

	svc_exit r5				@ return from exception

 UNWIND(.fnend		)

 UNWIND(.fnend		)

ENDPROC(__irq_svc)

ENDPROC(__irq_svc)
@@ -305,12 +293,6 @@ __und_svc_finish: 
	@ restore SPSR and restart the instruction

	@ restore SPSR and restart the instruction

	@

	@

	ldr	r5, [sp, #S_PSR]		@ Get SVC cpsr

	ldr	r5, [sp, #S_PSR]		@ Get SVC cpsr

#ifdef CONFIG_TRACE_IRQFLAGS

	tst	r5, #PSR_I_BIT

	bleq	trace_hardirqs_on

	tst	r5, #PSR_I_BIT

	blne	trace_hardirqs_off

#endif

	svc_exit r5				@ return from exception

	svc_exit r5				@ return from exception

 UNWIND(.fnend		)

 UNWIND(.fnend		)

ENDPROC(__und_svc)

ENDPROC(__und_svc)
@@ -325,13 +307,6 @@ __pabt_svc: 
	@ IRQs off again before pulling preserved data off the stack

	@ IRQs off again before pulling preserved data off the stack

	@

	@

	disable_irq_notrace

	disable_irq_notrace



#ifdef CONFIG_TRACE_IRQFLAGS

	tst	r5, #PSR_I_BIT

	bleq	trace_hardirqs_on

	tst	r5, #PSR_I_BIT

	blne	trace_hardirqs_off

#endif

	svc_exit r5				@ return from exception

	svc_exit r5				@ return from exception

 UNWIND(.fnend		)

 UNWIND(.fnend		)

ENDPROC(__pabt_svc)

ENDPROC(__pabt_svc)

arch/arm/kernel/entry-header.S

+30 −2
Original line number Original line Diff line number Diff line
@@ -74,7 +74,21 @@ 
	.endm

	.endm





#ifndef CONFIG_THUMB2_KERNEL

#ifndef CONFIG_THUMB2_KERNEL

	.macro	svc_exit, rpsr

	.macro	svc_exit, rpsr, irq = 0

	.if	\irq != 0

#ifdef CONFIG_TRACE_IRQFLAGS

	@ The parent context IRQs must have been enabled to get here in

	@ the first place, so there's no point checking the PSR I bit.

	bl	trace_hardirqs_on

#endif

	.else

#ifdef CONFIG_TRACE_IRQFLAGS

	tst	\rpsr, #PSR_I_BIT

	bleq	trace_hardirqs_on

	tst	\rpsr, #PSR_I_BIT

	blne	trace_hardirqs_off

#endif

	.endif

	msr	spsr_cxsf, \rpsr

	msr	spsr_cxsf, \rpsr

#if defined(CONFIG_CPU_V6)

#if defined(CONFIG_CPU_V6)

	ldr	r0, [sp]

	ldr	r0, [sp]
@@ -120,7 +134,21 @@ 
	mov	pc, \reg

	mov	pc, \reg

	.endm

	.endm

#else	/* CONFIG_THUMB2_KERNEL */

#else	/* CONFIG_THUMB2_KERNEL */

	.macro	svc_exit, rpsr

	.macro	svc_exit, rpsr, irq = 0

	.if	\irq != 0

#ifdef CONFIG_TRACE_IRQFLAGS

	@ The parent context IRQs must have been enabled to get here in

	@ the first place, so there's no point checking the PSR I bit.

	bl	trace_hardirqs_on

#endif

	.else

#ifdef CONFIG_TRACE_IRQFLAGS

	tst	\rpsr, #PSR_I_BIT

	bleq	trace_hardirqs_on

	tst	\rpsr, #PSR_I_BIT

	blne	trace_hardirqs_off

#endif

	.endif

	ldr	lr, [sp, #S_SP]			@ top of the stack

	ldr	lr, [sp, #S_SP]			@ top of the stack

	ldrd	r0, r1, [sp, #S_LR]		@ calling lr and pc

	ldrd	r0, r1, [sp, #S_LR]		@ calling lr and pc

	clrex					@ clear the exclusive monitor

	clrex					@ clear the exclusive monitor