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Commit 9b553f72 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux into drm-core-next 

* 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux: (72 commits)
  drm/i915/dp: Fix eDP on PCH DP on CPT/PPT
  drm/i915/dp: Introduce is_cpu_edp()
  drm/i915: use correct SPD type value
  drm/i915: fix ILK+ infoframe support
  drm/i915: add DP test request handling
  drm/i915: read full receiver capability field during DP hot plug
  drm/i915/dp: Remove eDP special cases from bandwidth checks
  drm/i915/dp: Fix the math in intel_dp_link_required
  drm/i915/panel: Always record the backlight level again (but cleverly)
  i915: Move i915_read/write out of line
  drm/i915: remove transcoder PLL mashing from mode_set per specs
  drm/i915: if transcoder disable fails, say which
  drm/i915: set watermarks for third pipe on IVB
  drm/i915: export a CPT mode set verification function
  drm/i915: fix transcoder PLL select masking
  drm/i915: fix IVB cursor support
  drm/i915: fix debug output for 3 pipe configs
  drm/i915: add PLL sharing support to handle 3 pipes
  drm/i915: fix PCH PLL assertion check for 3 pipes
  drm/i915: use transcoder select bits on VGA and HDMI on CPT
  ...
parents c5c42360 82d16555

drivers/char/agp/intel-gtt.c

+28 −0
Original line number Diff line number Diff line
@@ -923,6 +923,9 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, 
{

	int ret = -EINVAL;



	if (intel_private.base.do_idle_maps)

		return -ENODEV;



	if (intel_private.clear_fake_agp) {

		int start = intel_private.base.stolen_size / PAGE_SIZE;

		int end = intel_private.base.gtt_mappable_entries;
@@ -985,6 +988,9 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem, 
	if (mem->page_count == 0)

		return 0;



	if (intel_private.base.do_idle_maps)

		return -ENODEV;



	intel_gtt_clear_range(pg_start, mem->page_count);



	if (intel_private.base.needs_dmar) {
@@ -1177,6 +1183,25 @@ static void gen6_cleanup(void) 
{

}



/* Certain Gen5 chipsets require require idling the GPU before

 * unmapping anything from the GTT when VT-d is enabled.

 */

extern int intel_iommu_gfx_mapped;

static inline int needs_idle_maps(void)

{

	const unsigned short gpu_devid = intel_private.pcidev->device;



	/* Query intel_iommu to see if we need the workaround. Presumably that

	 * was loaded first.

	 */

	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||

	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&

	     intel_iommu_gfx_mapped)

		return 1;



	return 0;

}



static int i9xx_setup(void)

{

	u32 reg_addr;
@@ -1211,6 +1236,9 @@ static int i9xx_setup(void) 
		intel_private.gtt_bus_addr = reg_addr + gtt_offset;

	}



	if (needs_idle_maps());

		intel_private.base.do_idle_maps = 1;



	intel_i9xx_setup_flush();



	return 0;

drivers/gpu/drm/i915/i915_dma.c

+3 −1
Original line number Diff line number Diff line
@@ -2035,7 +2035,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->error_lock);

	spin_lock_init(&dev_priv->rps_lock);



	if (IS_MOBILE(dev) || !IS_GEN2(dev))

	if (IS_IVYBRIDGE(dev))

		dev_priv->num_pipe = 3;

	else if (IS_MOBILE(dev) || !IS_GEN2(dev))

		dev_priv->num_pipe = 2;

	else

		dev_priv->num_pipe = 1;

drivers/gpu/drm/i915/i915_drv.c

+45 −2
Original line number Diff line number Diff line
@@ -79,11 +79,11 @@ MODULE_PARM_DESC(lvds_downclock, 
		"Use panel (LVDS/eDP) downclocking for power savings "

		"(default: false)");



unsigned int i915_panel_use_ssc __read_mostly = 1;

unsigned int i915_panel_use_ssc __read_mostly = -1;

module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);

MODULE_PARM_DESC(lvds_use_ssc,

		"Use Spread Spectrum Clock with panels [LVDS/eDP] "

		"(default: true)");

		"(default: auto from VBT)");



int i915_vbt_sdvo_panel_type __read_mostly = -1;

module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
@@ -471,6 +471,9 @@ static int i915_drm_thaw(struct drm_device *dev) 
		error = i915_gem_init_ringbuffer(dev);

		mutex_unlock(&dev->struct_mutex);



		if (HAS_PCH_SPLIT(dev))

			ironlake_init_pch_refclk(dev);



		drm_mode_config_reset(dev);

		drm_irq_install(dev);
@@ -895,3 +898,43 @@ module_exit(i915_exit); 
MODULE_AUTHOR(DRIVER_AUTHOR);

MODULE_DESCRIPTION(DRIVER_DESC);

MODULE_LICENSE("GPL and additional rights");



/* We give fast paths for the really cool registers */

#define NEEDS_FORCE_WAKE(dev_priv, reg) \

	(((dev_priv)->info->gen >= 6) && \

	((reg) < 0x40000) && \

	((reg) != FORCEWAKE))



#define __i915_read(x, y) \

u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

	u##x val = 0; \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		gen6_gt_force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		gen6_gt_force_wake_put(dev_priv); \

	} else { \

		val = read##y(dev_priv->regs + reg); \

	} \

	trace_i915_reg_rw(false, reg, val, sizeof(val)); \

	return val; \

}



__i915_read(8, b)

__i915_read(16, w)

__i915_read(32, l)

__i915_read(64, q)

#undef __i915_read



#define __i915_write(x, y) \

void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \

	trace_i915_reg_rw(true, reg, val, sizeof(val)); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		__gen6_gt_wait_for_fifo(dev_priv); \

	} \

	write##y(val, dev_priv->regs + reg); \

}

__i915_write(8, b)

__i915_write(16, w)

__i915_write(32, l)

__i915_write(64, q)

#undef __i915_write

drivers/gpu/drm/i915/i915_drv.h

+7 −24
Original line number Diff line number Diff line
@@ -139,7 +139,6 @@ struct sdvo_device_mapping { 
	u8 slave_addr;

	u8 dvo_wiring;

	u8 i2c_pin;

	u8 i2c_speed;

	u8 ddc_pin;

};
@@ -349,7 +348,6 @@ typedef struct drm_i915_private { 
	/* LVDS info */

	int backlight_level;  /* restore backlight to this value */

	bool backlight_enabled;

	struct drm_display_mode *panel_fixed_mode;

	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -359,6 +357,7 @@ typedef struct drm_i915_private { 
	unsigned int lvds_vbt:1;

	unsigned int int_crt_support:1;

	unsigned int lvds_use_ssc:1;

	unsigned int display_clock_mode:1;

	int lvds_ssc_freq;

	struct {

		int rate;
@@ -674,10 +673,9 @@ typedef struct drm_i915_private { 
	unsigned int lvds_border_bits;

	/* Panel fitter placement and size for Ironlake+ */

	u32 pch_pf_pos, pch_pf_size;

	int panel_t3, panel_t12;



	struct drm_crtc *plane_to_crtc_mapping[2];

	struct drm_crtc *pipe_to_crtc_mapping[2];

	struct drm_crtc *plane_to_crtc_mapping[3];

	struct drm_crtc *pipe_to_crtc_mapping[3];

	wait_queue_head_t pending_flip_queue;

	bool flip_pending_is_done;
@@ -1303,6 +1301,7 @@ extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 
extern bool intel_fbc_enabled(struct drm_device *dev);

extern void intel_disable_fbc(struct drm_device *dev);

extern bool ironlake_set_drps(struct drm_device *dev, u8 val);

extern void ironlake_init_pch_refclk(struct drm_device *dev);

extern void ironlake_enable_rc6(struct drm_device *dev);

extern void gen6_set_rps(struct drm_device *dev, u8 val);

extern void intel_detect_pch(struct drm_device *dev);
@@ -1356,18 +1355,7 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 
	((reg) != FORCEWAKE))



#define __i915_read(x, y) \

static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

	u##x val = 0; \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		gen6_gt_force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		gen6_gt_force_wake_put(dev_priv); \

	} else { \

		val = read##y(dev_priv->regs + reg); \

	} \

	trace_i915_reg_rw(false, reg, val, sizeof(val)); \

	return val; \

}

	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);



__i915_read(8, b)

__i915_read(16, w)
@@ -1376,13 +1364,8 @@ __i915_read(64, q) 
#undef __i915_read



#define __i915_write(x, y) \

static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \

	trace_i915_reg_rw(true, reg, val, sizeof(val)); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		__gen6_gt_wait_for_fifo(dev_priv); \

	} \

	write##y(val, dev_priv->regs + reg); \

}

	void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);



__i915_write(8, b)

__i915_write(16, w)

__i915_write(32, l)

drivers/gpu/drm/i915/i915_gem.c

+6 −10
Original line number Diff line number Diff line
@@ -195,6 +195,8 @@ i915_gem_create(struct drm_file *file, 
	u32 handle;



	size = roundup(size, PAGE_SIZE);

	if (size == 0)

		return -EINVAL;



	/* Allocate the new object */

	obj = i915_gem_alloc_object(dev, size);
@@ -800,11 +802,11 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, 
		if (IS_ERR(page))

			return PTR_ERR(page);



		vaddr = kmap_atomic(page, KM_USER0);

		vaddr = kmap_atomic(page);

		ret = __copy_from_user_inatomic(vaddr + page_offset,

						user_data,

						page_length);

		kunmap_atomic(vaddr, KM_USER0);

		kunmap_atomic(vaddr);



		set_page_dirty(page);

		mark_page_accessed(page);
@@ -1476,7 +1478,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, 
		obj->pages[i] = page;

	}



	if (obj->tiling_mode != I915_TILING_NONE)

	if (i915_gem_object_needs_bit17_swizzle(obj))

		i915_gem_object_do_bit_17_swizzle(obj);



	return 0;
@@ -1498,7 +1500,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) 


	BUG_ON(obj->madv == __I915_MADV_PURGED);



	if (obj->tiling_mode != I915_TILING_NONE)

	if (i915_gem_object_needs_bit17_swizzle(obj))

		i915_gem_object_save_bit_17_swizzle(obj);



	if (obj->madv == I915_MADV_DONTNEED)
@@ -2191,14 +2193,8 @@ int 
i915_gpu_idle(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	bool lists_empty;

	int ret, i;



	lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&

		       list_empty(&dev_priv->mm.active_list));

	if (lists_empty)

		return 0;



	/* Flush everything onto the inactive list. */

	for (i = 0; i < I915_NUM_RINGS; i++) {

		ret = i915_ring_idle(&dev_priv->ring[i]);