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Commit 9abc9378 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.15-rc9' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Nouveau, i915, vmwgfx and sun4i regression fixes.

  The i915 change fixes a display corruption problem introduced in 4.15,
  the nouveau changes are for regressions in 4.15, one of the vmwgfx
  fixes goes back a little further, the other is a 4.15 regression fix,
  the 3 sun4i changes fix blank HDMI output on those devices"

* tag 'drm-fixes-for-v4.15-rc9' of git://people.freedesktop.org/~airlied/linux:
  drm/nouveau/mmu/mcp77: fix regressions in stolen memory handling
  drm/nouveau/bar/gk20a: Avoid bar teardown during init
  drm/nouveau/drm/nouveau: Pass the proper arguments to nvif_object_map_handle()
  drm/vmwgfx: fix memory corruption with legacy/sou connectors
  drm/vmwgfx: Fix a boot time warning
  drm/i915: Fix deadlock in i830_disable_pipe()
  drm/i915: Redo plane sanitation during readout
  drm/i915: Add .get_hw_state() method for planes
  drm/sun4i: hdmi: Add missing rate halving check in sun4i_tmds_determine_rate
  drm/sun4i: hdmi: Fix incorrect assignment in sun4i_tmds_determine_rate
  drm/sun4i: hdmi: Check for unset best_parent in sun4i_tmds_determine_rate
parents d342740e 04cef3ea

drivers/gpu/drm/i915/intel_display.c

+157 −146
Original line number Diff line number Diff line
@@ -1211,23 +1211,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) 
	     pipe_name(pipe));

}



static void assert_cursor(struct drm_i915_private *dev_priv,

			  enum pipe pipe, bool state)

{

	bool cur_state;



	if (IS_I845G(dev_priv) || IS_I865G(dev_priv))

		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;

	else

		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;



	I915_STATE_WARN(cur_state != state,

	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",

			pipe_name(pipe), onoff(state), onoff(cur_state));

}

#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)

#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)



void assert_pipe(struct drm_i915_private *dev_priv,

		 enum pipe pipe, bool state)

{
@@ -1255,77 +1238,25 @@ void assert_pipe(struct drm_i915_private *dev_priv, 
			pipe_name(pipe), onoff(state), onoff(cur_state));

}



static void assert_plane(struct drm_i915_private *dev_priv,

			 enum plane plane, bool state)

static void assert_plane(struct intel_plane *plane, bool state)

{

	u32 val;

	bool cur_state;

	bool cur_state = plane->get_hw_state(plane);



	val = I915_READ(DSPCNTR(plane));

	cur_state = !!(val & DISPLAY_PLANE_ENABLE);

	I915_STATE_WARN(cur_state != state,

	     "plane %c assertion failure (expected %s, current %s)\n",

			plane_name(plane), onoff(state), onoff(cur_state));

			"%s assertion failure (expected %s, current %s)\n",

			plane->base.name, onoff(state), onoff(cur_state));

}



#define assert_plane_enabled(d, p) assert_plane(d, p, true)

#define assert_plane_disabled(d, p) assert_plane(d, p, false)

#define assert_plane_enabled(p) assert_plane(p, true)

#define assert_plane_disabled(p) assert_plane(p, false)



static void assert_planes_disabled(struct drm_i915_private *dev_priv,

				   enum pipe pipe)

static void assert_planes_disabled(struct intel_crtc *crtc)

{

	int i;



	/* Primary planes are fixed to pipes on gen4+ */

	if (INTEL_GEN(dev_priv) >= 4) {

		u32 val = I915_READ(DSPCNTR(pipe));

		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,

		     "plane %c assertion failure, should be disabled but not\n",

		     plane_name(pipe));

		return;

	}

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_plane *plane;



	/* Need to check both planes against the pipe */

	for_each_pipe(dev_priv, i) {

		u32 val = I915_READ(DSPCNTR(i));

		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>

			DISPPLANE_SEL_PIPE_SHIFT;

		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,

		     "plane %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(i), pipe_name(pipe));

	}

}



static void assert_sprites_disabled(struct drm_i915_private *dev_priv,

				    enum pipe pipe)

{

	int sprite;



	if (INTEL_GEN(dev_priv) >= 9) {

		for_each_sprite(dev_priv, pipe, sprite) {

			u32 val = I915_READ(PLANE_CTL(pipe, sprite));

			I915_STATE_WARN(val & PLANE_CTL_ENABLE,

			     "plane %d assertion failure, should be off on pipe %c but is still active\n",

			     sprite, pipe_name(pipe));

		}

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		for_each_sprite(dev_priv, pipe, sprite) {

			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));

			I915_STATE_WARN(val & SP_ENABLE,

			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

			     sprite_name(pipe, sprite), pipe_name(pipe));

		}

	} else if (INTEL_GEN(dev_priv) >= 7) {

		u32 val = I915_READ(SPRCTL(pipe));

		I915_STATE_WARN(val & SPRITE_ENABLE,

		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(pipe), pipe_name(pipe));

	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {

		u32 val = I915_READ(DVSCNTR(pipe));

		I915_STATE_WARN(val & DVS_ENABLE,

		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(pipe), pipe_name(pipe));

	}

	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)

		assert_plane_disabled(plane);

}



static void assert_vblank_disabled(struct drm_crtc *crtc)
@@ -1918,9 +1849,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) 


	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));



	assert_planes_disabled(dev_priv, pipe);

	assert_cursor_disabled(dev_priv, pipe);

	assert_sprites_disabled(dev_priv, pipe);

	assert_planes_disabled(crtc);



	/*

	 * A pipe without a PLL won't actually be able to drive bits from
@@ -1989,9 +1918,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) 
	 * Make sure planes won't keep trying to pump pixels to us,

	 * or we might hang the display.

	 */

	assert_planes_disabled(dev_priv, pipe);

	assert_cursor_disabled(dev_priv, pipe);

	assert_sprites_disabled(dev_priv, pipe);

	assert_planes_disabled(crtc);



	reg = PIPECONF(cpu_transcoder);

	val = I915_READ(reg);
@@ -2820,6 +2747,23 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state, 
		      crtc_state->active_planes);

}



static void intel_plane_disable_noatomic(struct intel_crtc *crtc,

					 struct intel_plane *plane)

{

	struct intel_crtc_state *crtc_state =

		to_intel_crtc_state(crtc->base.state);

	struct intel_plane_state *plane_state =

		to_intel_plane_state(plane->base.state);



	intel_set_plane_visible(crtc_state, plane_state, false);



	if (plane->id == PLANE_PRIMARY)

		intel_pre_disable_primary_noatomic(&crtc->base);



	trace_intel_disable_plane(&plane->base, crtc);

	plane->disable_plane(plane, crtc);

}



static void

intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,

			     struct intel_initial_plane_config *plane_config)
@@ -2877,12 +2821,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, 
	 * simplest solution is to just disable the primary plane now and

	 * pretend the BIOS never had it enabled.

	 */

	intel_set_plane_visible(to_intel_crtc_state(crtc_state),

				to_intel_plane_state(plane_state),

				false);

	intel_pre_disable_primary_noatomic(&intel_crtc->base);

	trace_intel_disable_plane(primary, intel_crtc);

	intel_plane->disable_plane(intel_plane, intel_crtc);

	intel_plane_disable_noatomic(intel_crtc, intel_plane);



	return;
@@ -3385,6 +3324,31 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary, 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool i9xx_plane_get_hw_state(struct intel_plane *primary)

{



	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane plane = primary->plane;

	enum pipe pipe = primary->pipe;

	bool ret;



	/*

	 * Not 100% correct for planes that can move between pipes,

	 * but that's only the case for gen2-4 which don't have any

	 * display power wells.

	 */

	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32

intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)

{
@@ -4866,7 +4830,8 @@ void hsw_enable_ips(struct intel_crtc *crtc) 
	 * a vblank wait.

	 */



	assert_plane_enabled(dev_priv, crtc->plane);

	assert_plane_enabled(to_intel_plane(crtc->base.primary));



	if (IS_BROADWELL(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
@@ -4899,7 +4864,8 @@ void hsw_disable_ips(struct intel_crtc *crtc) 
	if (!crtc->config->ips_enabled)

		return;



	assert_plane_enabled(dev_priv, crtc->plane);

	assert_plane_enabled(to_intel_plane(crtc->base.primary));



	if (IS_BROADWELL(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
@@ -5899,6 +5865,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

	enum intel_display_power_domain domain;

	struct intel_plane *plane;

	u64 domains;

	struct drm_atomic_state *state;

	struct intel_crtc_state *crtc_state;
@@ -5907,11 +5874,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, 
	if (!intel_crtc->active)

		return;



	if (crtc->primary->state->visible) {

		intel_pre_disable_primary_noatomic(crtc);

	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {

		const struct intel_plane_state *plane_state =

			to_intel_plane_state(plane->base.state);



		intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));

		crtc->primary->state->visible = false;

		if (plane_state->base.visible)

			intel_plane_disable_noatomic(intel_crtc, plane);

	}



	state = drm_atomic_state_alloc(crtc->dev);
@@ -9477,6 +9445,23 @@ static void i845_disable_cursor(struct intel_plane *plane, 
	i845_update_cursor(plane, NULL, NULL);

}



static bool i845_cursor_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(PIPE_A);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,

			   const struct intel_plane_state *plane_state)

{
@@ -9670,6 +9655,28 @@ static void i9xx_disable_cursor(struct intel_plane *plane, 
	i9xx_update_cursor(plane, NULL, NULL);

}



static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	/*

	 * Not 100% correct for planes that can move between pipes,

	 * but that's only the case for gen2-3 which don't have any

	 * display power wells.

	 */

	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



/* VESA 640x480x72Hz mode to set on the pipe */

static const struct drm_display_mode load_detect_mode = {
@@ -13205,6 +13212,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = skl_update_plane;

		primary->disable_plane = skl_disable_plane;

		primary->get_hw_state = skl_plane_get_hw_state;

	} else if (INTEL_GEN(dev_priv) >= 9) {

		intel_primary_formats = skl_primary_formats;

		num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13215,6 +13223,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = skl_update_plane;

		primary->disable_plane = skl_disable_plane;

		primary->get_hw_state = skl_plane_get_hw_state;

	} else if (INTEL_GEN(dev_priv) >= 4) {

		intel_primary_formats = i965_primary_formats;

		num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -13222,6 +13231,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = i9xx_update_primary_plane;

		primary->disable_plane = i9xx_disable_primary_plane;

		primary->get_hw_state = i9xx_plane_get_hw_state;

	} else {

		intel_primary_formats = i8xx_primary_formats;

		num_formats = ARRAY_SIZE(i8xx_primary_formats);
@@ -13229,6 +13239,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = i9xx_update_primary_plane;

		primary->disable_plane = i9xx_disable_primary_plane;

		primary->get_hw_state = i9xx_plane_get_hw_state;

	}



	if (INTEL_GEN(dev_priv) >= 9)
@@ -13318,10 +13329,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, 
	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {

		cursor->update_plane = i845_update_cursor;

		cursor->disable_plane = i845_disable_cursor;

		cursor->get_hw_state = i845_cursor_get_hw_state;

		cursor->check_plane = i845_check_cursor;

	} else {

		cursor->update_plane = i9xx_update_cursor;

		cursor->disable_plane = i9xx_disable_cursor;

		cursor->get_hw_state = i9xx_cursor_get_hw_state;

		cursor->check_plane = i9xx_check_cursor;

	}
@@ -14671,8 +14684,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
	DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",

		      pipe_name(pipe));



	assert_plane_disabled(dev_priv, PLANE_A);

	assert_plane_disabled(dev_priv, PLANE_B);

	WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);

	WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);

	WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);

	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);

	WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);



	I915_WRITE(PIPECONF(pipe), 0);

	POSTING_READ(PIPECONF(pipe));
@@ -14683,22 +14699,36 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
	POSTING_READ(DPLL(pipe));

}



static bool

intel_check_plane_mapping(struct intel_crtc *crtc)

static bool intel_plane_mapping_ok(struct intel_crtc *crtc,

				   struct intel_plane *primary)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 val;

	enum plane plane = primary->plane;

	u32 val = I915_READ(DSPCNTR(plane));



	if (INTEL_INFO(dev_priv)->num_pipes == 1)

		return true;

	return (val & DISPLAY_PLANE_ENABLE) == 0 ||

		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);

}



	val = I915_READ(DSPCNTR(!crtc->plane));

static void

intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)

{

	struct intel_crtc *crtc;



	if ((val & DISPLAY_PLANE_ENABLE) &&

	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))

		return false;

	if (INTEL_GEN(dev_priv) >= 4)

		return;



	return true;

	for_each_intel_crtc(&dev_priv->drm, crtc) {

		struct intel_plane *plane =

			to_intel_plane(crtc->base.primary);



		if (intel_plane_mapping_ok(crtc, plane))

			continue;



		DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",

			      plane->base.name);

		intel_plane_disable_noatomic(crtc, plane);

	}

}



static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
@@ -14754,33 +14784,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, 


		/* Disable everything but the primary plane */

		for_each_intel_plane_on_crtc(dev, crtc, plane) {

			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)

				continue;

			const struct intel_plane_state *plane_state =

				to_intel_plane_state(plane->base.state);



			trace_intel_disable_plane(&plane->base, crtc);

			plane->disable_plane(plane, crtc);

			if (plane_state->base.visible &&

			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)

				intel_plane_disable_noatomic(crtc, plane);

		}

	}



	/* We need to sanitize the plane -> pipe mapping first because this will

	 * disable the crtc (and hence change the state) if it is wrong. Note

	 * that gen4+ has a fixed plane -> pipe mapping.  */

	if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {

		bool plane;



		DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",

			      crtc->base.base.id, crtc->base.name);



		/* Pipe has the wrong plane attached and the plane is active.

		 * Temporarily change the plane mapping and disable everything

		 * ...  */

		plane = crtc->plane;

		crtc->base.primary->state->visible = true;

		crtc->plane = !plane;

		intel_crtc_disable_noatomic(&crtc->base, ctx);

		crtc->plane = plane;

	}



	/* Adjust the state of the output pipe according to whether we

	 * have active connectors/encoders. */

	if (crtc->active && !intel_crtc_has_encoders(crtc))
@@ -14885,24 +14897,21 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) 
	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

}



static bool primary_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);



	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;

}



/* FIXME read out full plane state for all planes */

static void readout_plane_state(struct intel_crtc *crtc)

{

	struct intel_plane *primary = to_intel_plane(crtc->base.primary);

	bool visible;

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_crtc_state *crtc_state =

		to_intel_crtc_state(crtc->base.state);

	struct intel_plane *plane;



	visible = crtc->active && primary_get_hw_state(primary);

	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {

		struct intel_plane_state *plane_state =

			to_intel_plane_state(plane->base.state);

		bool visible = plane->get_hw_state(plane);



	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),

				to_intel_plane_state(primary->base.state),

				visible);

		intel_set_plane_visible(crtc_state, plane_state, visible);

	}

}



static void intel_modeset_readout_hw_state(struct drm_device *dev)
@@ -15100,6 +15109,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev, 
	/* HW state is read out, now we need to sanitize this mess. */

	get_encoder_power_domains(dev_priv);



	intel_sanitize_plane_mapping(dev_priv);



	for_each_intel_encoder(dev, encoder) {

		intel_sanitize_encoder(encoder);

	}

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -862,6 +862,7 @@ struct intel_plane { 
			     const struct intel_plane_state *plane_state);

	void (*disable_plane)(struct intel_plane *plane,

			      struct intel_crtc *crtc);

	bool (*get_hw_state)(struct intel_plane *plane);

	int (*check_plane)(struct intel_plane *plane,

			   struct intel_crtc_state *crtc_state,

			   struct intel_plane_state *state);
@@ -1924,6 +1925,7 @@ void skl_update_plane(struct intel_plane *plane, 
		      const struct intel_crtc_state *crtc_state,

		      const struct intel_plane_state *plane_state);

void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);

bool skl_plane_get_hw_state(struct intel_plane *plane);



/* intel_tv.c */

void intel_tv_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_sprite.c

+83 −0
Original line number Diff line number Diff line
@@ -329,6 +329,26 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



bool

skl_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static void

chv_update_csc(struct intel_plane *plane, uint32_t format)

{
@@ -506,6 +526,26 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

vlv_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,

			  const struct intel_plane_state *plane_state)

{
@@ -646,6 +686,25 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

ivb_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,

			  const struct intel_plane_state *plane_state)

{
@@ -777,6 +836,25 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

g4x_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static int

intel_check_sprite_plane(struct intel_plane *plane,

			 struct intel_crtc_state *crtc_state,
@@ -1232,6 +1310,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = skl_update_plane;

		intel_plane->disable_plane = skl_disable_plane;

		intel_plane->get_hw_state = skl_plane_get_hw_state;



		plane_formats = skl_plane_formats;

		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1242,6 +1321,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = skl_update_plane;

		intel_plane->disable_plane = skl_disable_plane;

		intel_plane->get_hw_state = skl_plane_get_hw_state;



		plane_formats = skl_plane_formats;

		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1252,6 +1332,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = vlv_update_plane;

		intel_plane->disable_plane = vlv_disable_plane;

		intel_plane->get_hw_state = vlv_plane_get_hw_state;



		plane_formats = vlv_plane_formats;

		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
@@ -1267,6 +1348,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = ivb_update_plane;

		intel_plane->disable_plane = ivb_disable_plane;

		intel_plane->get_hw_state = ivb_plane_get_hw_state;



		plane_formats = snb_plane_formats;

		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1277,6 +1359,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = g4x_update_plane;

		intel_plane->disable_plane = g4x_disable_plane;

		intel_plane->get_hw_state = g4x_plane_get_hw_state;



		modifiers = i9xx_plane_format_modifiers;

		if (IS_GEN6(dev_priv)) {

drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); 
int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int g84_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int mcp77_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int gk104_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

int gk20a_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);

drivers/gpu/drm/nouveau/nouveau_bo.c

+3 −1
Original line number Diff line number Diff line
@@ -1447,11 +1447,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 
				args.nv50.ro = 0;

				args.nv50.kind = mem->kind;

				args.nv50.comp = mem->comp;

				argc = sizeof(args.nv50);

				break;

			case NVIF_CLASS_MEM_GF100:

				args.gf100.version = 0;

				args.gf100.ro = 0;

				args.gf100.kind = mem->kind;

				argc = sizeof(args.gf100);

				break;

			default:

				WARN_ON(1);
@@ -1459,7 +1461,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 
			}



			ret = nvif_object_map_handle(&mem->mem.object,

						     &argc, argc,

						     &args, argc,

						     &handle, &length);

			if (ret != 1)

				return ret ? ret : -EINVAL;