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Commit 9abafa02 authored by Stephen Warren's avatar Stephen Warren
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ARM: tegra: change pll_p_out4's rate to 24MHz 



pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: default avatarMarc Dietrich <marvin24@gmx.de>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 7ff4db09

arch/arm/mach-tegra/board-paz00.c

+0 −1
Original line number Diff line number Diff line
@@ -176,7 +176,6 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 
	{ "uarta",	"pll_p",	216000000,	true },

	{ "uartc",	"pll_p",	216000000,	true },



	{ "pll_p_out4",	"pll_p",	24000000,	true },

	{ "usbd",	"clk_m",	12000000,	false },

	{ "usb2",	"clk_m",	12000000,	false },

	{ "usb3",	"clk_m",	12000000,	false },

arch/arm/mach-tegra/common.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { 
	{ "pll_p_out1",	"pll_p",	28800000,	true },

	{ "pll_p_out2",	"pll_p",	48000000,	true },

	{ "pll_p_out3",	"pll_p",	72000000,	true },

	{ "pll_p_out4",	"pll_p",	108000000,	true },

	{ "pll_p_out4",	"pll_p",	24000000,	true },

	{ "pll_c",	"clk_m",	600000000,	true },

	{ "pll_c_out1",	"pll_c",	120000000,	true },

	{ "sclk",	"pll_c_out1",	120000000,	true },