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Commit 9a902bb5 authored by Mohammed Nayeem Ur Rahman's avatar Mohammed Nayeem Ur Rahman
Browse files

ARM: dts: msm: update lagoon DT entries for fastRPC usecases 



Add CDSP loader DT entry to load CDSP image, add adsprpc mem
region DT entry for remote heap usecase, configure SMMU context
banks for fastRPC sessions.

Acked-by: default avatarMaitreyi Gupta <maitreyi@qti.qualcomm.com>
Change-Id: I42a192d6eb26847bec01c31d7c1a9f9aa16a8b52
parent e486dfbf

qcom/lagoon.dtsi

+139 −0
Original line number Diff line number Diff line
@@ -495,6 +495,14 @@ 
			no-map;

		};



		adsp_mem: adsp_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x800000>;

		};



		/* global autoconfigured region for contiguous allocations */

		linux,cma {

			compatible = "shared-dma-pool";
@@ -1356,6 +1364,137 @@ 
		hwlocks = <&tcsr_mutex 3>;

	};



	qcom,msm-cdsp-loader {

		compatible = "qcom,cdsp-loader";

		qcom,proc-img-to-load = "cdsp";

	};



	qcom,msm-adsprpc-mem {

		compatible = "qcom,msm-adsprpc-mem-region";

		memory-region = <&adsp_mem>;

		restrict-access;

	};



	qcom,msm_fastrpc {

		compatible = "qcom,msm-fastrpc-compute";

		qcom,adsp-remoteheap-vmid = <22 37>;

		qcom,fastrpc-adsp-audio-pdr;

		qcom,fastrpc-adsp-sensors-pdr;

		qcom,rpc-latency-us = <235>;

		qcom,qos-cores = <0 1 2 3 4 5>;



		qcom,msm_fastrpc_compute_cb1 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1401 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb2 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1402 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb3 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1403 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb4 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1404 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb5 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1405 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb6 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1406 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb7 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1407 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb8 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1408 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb9 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			qcom,secure-context-bank;

			iommus = <&apps_smmu 0x1409 0x0020>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-vmid = <0xA>;

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb10 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1003 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb11 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1004 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};



		qcom,msm_fastrpc_compute_cb12 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1005 0x0>;

			shared-cb  = <5>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			dma-coherent;

		};

	};



	qcom,glink {

		compatible = "qcom,glink";

		#address-cells = <1>;