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Commit 9a2c13d6 authored by Vipin Deep Kaur's avatar Vipin Deep Kaur
Browse files

ARM: dts: msm: Add QUPV3 SE dt node for uart on kona 



Add initial device tree node for QUPV3 uart instance to support
serial console on se2 for RUMI and se12 from MTP.

Change-Id: Ibc78737c81f20158b8d9dda9fcd13e05e0bb6418
Signed-off-by: default avatarVipin Deep Kaur <vkaur@codeaurora.org>
parent 846dbfa1

arch/arm64/boot/dts/qcom/kona-cdp.dtsi

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@@ -7,3 +7,6 @@ 
#include "kona-pmic-overlay.dtsi"

#include "kona-camera-sensor-cdp.dtsi"



&qupv3_se12_2uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/kona-mtp.dtsi

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@@ -7,3 +7,6 @@ 
#include "kona-pmic-overlay.dtsi"

#include "kona-camera-sensor-mtp.dtsi"



&qupv3_se12_2uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi

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@@ -13,6 +13,62 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;



		qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {

			qupv3_se2_2uart_active: qupv3_se2_2uart_active {

				mux {

					pins = "gpio117", "gpio118";

					function = "qup2";

				};



				config {

					pins = "gpio117", "gpio118";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {

				mux {

					pins = "gpio117", "gpio118";

					function = "gpio";

				};



				config {

					pins = "gpio117", "gpio118";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {

			qupv3_se12_2uart_active: qupv3_se12_2uart_active {

				mux {

					pins = "gpio34", "gpio35";

					function = "qup12";

				};



				config {

					pins = "gpio34", "gpio35";

					drive-strength = <2>;

				};

			};



			qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep {

				mux {

					pins = "gpio34", "gpio35";

					drive-strength = <2>;

					bias-pull-down;

				};



				config {

					pins = "gpio34", "gpio35";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		ufs_dev_reset_assert: ufs_dev_reset_assert {

			config {

				pins = "ufs_reset";

arch/arm64/boot/dts/qcom/kona-qrd.dtsi

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@@ -4,3 +4,7 @@ 
 */



#include "kona-pmic-overlay.dtsi"



&qupv3_se12_2uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/kona-qupv3.dtsi

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/* QUPv3_0  wrapper  instance : North QUP*/

	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x9c0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x5a3 0x0>;

			qcom,iommu-dma = "disabled";

		};

	};



	/* Debug UART Instance for RUMI platform */

	qupv3_se2_2uart: qcom,qup_uart@988000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x988000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_2uart_active>;

		pinctrl-1 = <&qupv3_se2_2uart_sleep>;

		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* QUPv3_1  wrapper  instance : South_1 QUP */

	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0xac0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x43 0x0>;

			qcom,iommu-dma = "disabled";

		};

	};



	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se12_2uart: qcom,qup_uart@a90000 {

		compatible = "qcom,msm-geni-console";

		reg = <0xa90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se12_2uart_active>;

		pinctrl-1 = <&qupv3_se12_2uart_sleep>;

		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* QUPv3_2  wrapper  instance : South_2 QUP */

	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x8c0000 0x2000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;



		qcom,iommu-s1-bypass;

		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x63 0x0>;

			qcom,iommu-dma = "disabled";

		};

	};

};