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Commit 9a21e55d authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: dts: socfpga: update L2 tag and data latency 



Sets the appropriate L2-cache latencies for the SOCFPGA platform.

Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
parent 374b1057

arch/arm/boot/dts/socfpga.dtsi

+2 −0
Original line number Original line Diff line number Diff line
@@ -467,6 +467,8 @@ 
			interrupts = <0 38 0x04>;

			interrupts = <0 38 0x04>;

			cache-unified;

			cache-unified;

			cache-level = <2>;

			cache-level = <2>;

			arm,tag-latency = <1 1 1>;

			arm,data-latency = <2 1 1>;

		};

		};





		/* Local timer */

		/* Local timer */