Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9a1651dc authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

cpufreq: remove cris specific drivers 



The cris architecture is getting removed, including the artpec3
and etraxfs SoCs, so these cpufreq drivers are now unused.

Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Acked-by: default avatarRafael J. Wysocki <rafael@kernel.org>
Acked-by: default avatarJesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 9a3daf58

drivers/cpufreq/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -101,8 +101,6 @@ obj-$(CONFIG_POWERNV_CPUFREQ) += powernv-cpufreq.o 
##################################################################################

# Other platform drivers

obj-$(CONFIG_BMIPS_CPUFREQ)		+= bmips-cpufreq.o

obj-$(CONFIG_CRIS_MACH_ARTPEC3)		+= cris-artpec3-cpufreq.o

obj-$(CONFIG_ETRAXFS)			+= cris-etraxfs-cpufreq.o

obj-$(CONFIG_IA64_ACPI_CPUFREQ)		+= ia64-acpi-cpufreq.o

obj-$(CONFIG_LOONGSON2_CPUFREQ)		+= loongson2_cpufreq.o

obj-$(CONFIG_LOONGSON1_CPUFREQ)		+= loongson1-cpufreq.o

drivers/cpufreq/cris-artpec3-cpufreq.c

deleted100644 → 0
+0 −93
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include <linux/init.h>

#include <linux/module.h>

#include <linux/cpufreq.h>

#include <hwregs/reg_map.h>

#include <hwregs/reg_rdwr.h>

#include <hwregs/clkgen_defs.h>

#include <hwregs/ddr2_defs.h>



static int

cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,

	void *data);



static struct notifier_block cris_sdram_freq_notifier_block = {

	.notifier_call = cris_sdram_freq_notifier

};



static struct cpufreq_frequency_table cris_freq_table[] = {

	{0, 0x01, 6000},

	{0, 0x02, 200000},

	{0, 0, CPUFREQ_TABLE_END},

};



static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)

{

	reg_clkgen_rw_clk_ctrl clk_ctrl;

	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);

	return clk_ctrl.pll ? 200000 : 6000;

}



static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state)

{

	reg_clkgen_rw_clk_ctrl clk_ctrl;

	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);



	local_irq_disable();



	/* Even though we may be SMP they will share the same clock

	 * so all settings are made on CPU0. */

	if (cris_freq_table[state].frequency == 200000)

		clk_ctrl.pll = 1;

	else

		clk_ctrl.pll = 0;

	REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);



	local_irq_enable();



	return 0;

}



static int cris_freq_cpu_init(struct cpufreq_policy *policy)

{

	return cpufreq_generic_init(policy, cris_freq_table, 1000000);

}



static struct cpufreq_driver cris_freq_driver = {

	.get	= cris_freq_get_cpu_frequency,

	.verify	= cpufreq_generic_frequency_table_verify,

	.target_index = cris_freq_target,

	.init	= cris_freq_cpu_init,

	.name	= "cris_freq",

	.attr	= cpufreq_generic_attr,

};



static int __init cris_freq_init(void)

{

	int ret;

	ret = cpufreq_register_driver(&cris_freq_driver);

	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,

		CPUFREQ_TRANSITION_NOTIFIER);

	return ret;

}



static int

cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,

	void *data)

{

	int i;

	struct cpufreq_freqs *freqs = data;

	if (val == CPUFREQ_PRECHANGE) {

		reg_ddr2_rw_cfg cfg =

		  REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);

		cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);



		if (freqs->new == 200000)

			for (i = 0; i < 50000; i++);

		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);

	}

	return 0;

}





module_init(cris_freq_init);

drivers/cpufreq/cris-etraxfs-cpufreq.c

deleted100644 → 0
+0 −92
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include <linux/init.h>

#include <linux/module.h>

#include <linux/cpufreq.h>

#include <hwregs/reg_map.h>

#include <arch/hwregs/reg_rdwr.h>

#include <arch/hwregs/config_defs.h>

#include <arch/hwregs/bif_core_defs.h>



static int

cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,

			 void *data);



static struct notifier_block cris_sdram_freq_notifier_block = {

	.notifier_call = cris_sdram_freq_notifier

};



static struct cpufreq_frequency_table cris_freq_table[] = {

	{0, 0x01, 6000},

	{0, 0x02, 200000},

	{0, 0, CPUFREQ_TABLE_END},

};



static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)

{

	reg_config_rw_clk_ctrl clk_ctrl;

	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);

	return clk_ctrl.pll ? 200000 : 6000;

}



static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state)

{

	reg_config_rw_clk_ctrl clk_ctrl;

	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);



	local_irq_disable();



	/* Even though we may be SMP they will share the same clock

	 * so all settings are made on CPU0. */

	if (cris_freq_table[state].frequency == 200000)

		clk_ctrl.pll = 1;

	else

		clk_ctrl.pll = 0;

	REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);



	local_irq_enable();



	return 0;

}



static int cris_freq_cpu_init(struct cpufreq_policy *policy)

{

	return cpufreq_generic_init(policy, cris_freq_table, 1000000);

}



static struct cpufreq_driver cris_freq_driver = {

	.get = cris_freq_get_cpu_frequency,

	.verify = cpufreq_generic_frequency_table_verify,

	.target_index = cris_freq_target,

	.init = cris_freq_cpu_init,

	.name = "cris_freq",

	.attr = cpufreq_generic_attr,

};



static int __init cris_freq_init(void)

{

	int ret;

	ret = cpufreq_register_driver(&cris_freq_driver);

	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,

				  CPUFREQ_TRANSITION_NOTIFIER);

	return ret;

}



static int

cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,

			 void *data)

{

	int i;

	struct cpufreq_freqs *freqs = data;

	if (val == CPUFREQ_PRECHANGE) {

		reg_bif_core_rw_sdram_timing timing =

		    REG_RD(bif_core, regi_bif_core, rw_sdram_timing);

		timing.cpd = (freqs->new == 200000 ? 0 : 1);



		if (freqs->new == 200000)

			for (i = 0; i < 50000; i++) ;

		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);

	}

	return 0;

}



module_init(cris_freq_init);