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Commit 998b4ca7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dt-for-v4.1' of... 

Merge tag 'renesas-dt-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Renesas ARM Based SoC DT Updates for v4.1" from Simon Horman:

* Increase hardware coverage of DT for various SoCs
* Add PFC information for emev2 SoC
* Remap entire APMU region for r8a7791 and r8a7790 SoCs
* Declare the full 512 MiB of RAM for kzm9g board
* Add selectable sources to DIV6 clocks to sh73a0 SoC
* Add missing INTCA0 clock for irqpin module on sh73a0 SoC
* Set control-parent for all irqpin node on sh73a0 SoC

* tag 'renesas-dt-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
  ARM: shmobile: r8a7794: add SDHI DT support
  ARM: shmobile: r8a7790: add ADSP clocks
  ARM: shmobile: r8a7791: add ADSP clocks
  ARM: shmobile: henninger: add CAN0 DT support
  ARM: shmobile: r8a7791: add CAN DT support
  ARM: shmobile: r8a7791: add CAN clocks
  ARM: shmobile: r8a7790: add CAN DT support
  ARM: shmobile: r8a7790: add CAN clocks
  ARM: shmobile: emev2-kzm9d dts: Add PFC information for uart1
  ARM: shmobile: emev2 dtsi: Add PFC information
  ARM: shmobile: r8a7791: smp: remap whole apmu region
  ARM: shmobile: r8a7790: smp: remap whole apmu region
  ARM: shmobile: koelsch: Add DU HDMI output support
  ARM: shmobile: r8a7791: Correct SDHI clock labels and output-names
  ARM: shmobile: r8a7794: Correct SDHI clock base address, labels and output-names
  ARM: shmobile: r8a7794: alt: Enable ethernet controller
  ARM: shmobile: r8a7794: Add ethernet controller to device tree
  ARM: shmobile: r8a7794: Add IPMMU DT nodes
  ARM: shmobile: r8a7791: Add IPMMU DT nodes
  ARM: shmobile: r8a7790: Add IPMMU DT nodes
  ...
parents 13a7a6ac b8e8ea12

arch/arm/boot/dts/emev2-kzm9d.dts

+13 −0
Original line number Diff line number Diff line
@@ -94,3 +94,16 @@ 
		vdd33a-supply = <&reg_3p3v>;

	};

};



&pfc {

	uart1_pins: uart@e1030000 {

		renesas,groups = "uart1_ctrl", "uart1_data";

		renesas,function = "uart1";

	};

};



&uart1 {

	pinctrl-0 = <&uart1_pins>;

	pinctrl-names = "default";

	status = "okay";

};

arch/arm/boot/dts/emev2.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -169,12 +169,18 @@ 
		clock-names = "sclk";

	};



	pfc: pfc@e0140200 {

		compatible = "renesas,pfc-emev2";

		reg = <0xe0140200 0x100>;

	};



	gpio0: gpio@e0050000 {

		compatible = "renesas,em-gio";

		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;

		interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,

			     <0 68 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-ranges = <&pfc 0 0 32>;

		#gpio-cells = <2>;

		ngpios = <32>;

		interrupt-controller;
@@ -186,6 +192,7 @@ 
		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,

			     <0 70 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-ranges = <&pfc 0 32 32>;

		#gpio-cells = <2>;

		ngpios = <32>;

		interrupt-controller;
@@ -197,6 +204,7 @@ 
		interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,

			     <0 72 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-ranges = <&pfc 0 64 32>;

		#gpio-cells = <2>;

		ngpios = <32>;

		interrupt-controller;
@@ -208,6 +216,7 @@ 
		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,

			     <0 74 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-ranges = <&pfc 0 96 32>;

		#gpio-cells = <2>;

		ngpios = <32>;

		interrupt-controller;
@@ -219,6 +228,7 @@ 
		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,

			     <0 76 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		gpio-ranges = <&pfc 0 128 31>;

		#gpio-cells = <2>;

		ngpios = <31>;

		interrupt-controller;

arch/arm/boot/dts/r8a7740.dtsi

+78 −1
Original line number Diff line number Diff line
@@ -431,6 +431,18 @@ 
			clock-frequency = <27000000>;

			clock-output-names = "dv";

		};

		fmsick_clk: fmsick_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "fmsick";

		};

		fmsock_clk: fmsock_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "fmsock";

		};

		fsiack_clk: fsiack_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;
@@ -459,13 +471,78 @@ 
		};



		/* Variable factor clocks (DIV6) */

		vclk1_clk: vclk1_clk@e6150008 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150008 4>;

			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>,

				 <&extal1_div2_clk>, <&extalr_clk>, <0>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk1";

		};

		vclk2_clk: vclk2_clk@e615000c {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe615000c 4>;

			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>,

				 <&extal1_div2_clk>, <&extalr_clk>, <0>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk2";

		};

		fmsi_clk: fmsi_clk@e6150010 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150010 4>;

			clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fmsi";

		};

		fmso_clk: fmso_clk@e6150014 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150014 4>;

			clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fmso";

		};

		fsia_clk: fsia_clk@e6150018 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150018 4>;

			clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fsia";

		};

		sub_clk: sub_clk@e6150080 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150080 4>;

			clocks = <&pllc1_div2_clk>;

			clocks = <&pllc1_div2_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "sub";

		};

		spu_clk: spu_clk@e6150084 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150084 4>;

			clocks = <&pllc1_div2_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "spu";

		};

		vou_clk: vou_clk@e6150088 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150088 4>;

			clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vou";

		};

		stpro_clk: stpro_clk@e615009c {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe615009c 4>;

			clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;

			#clock-cells = <0>;

			clock-output-names = "stpro";

		};



		/* Fixed factor clocks */

		pllc1_div2_clk: pllc1_div2_clk {

arch/arm/boot/dts/r8a7790.dtsi

+97 −5
Original line number Diff line number Diff line
@@ -792,6 +792,26 @@ 
		};

	};



	can0: can@e6e80000 {

		compatible = "renesas,can-r8a7790";

		reg = <0 0xe6e80000 0 0x1000>;

		interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,

			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;

		clock-names = "clkp1", "clkp2", "can_clk";

		status = "disabled";

	};



	can1: can@e6e88000 {

		compatible = "renesas,can-r8a7790";

		reg = <0 0xe6e88000 0 0x1000>;

		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,

			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;

		clock-names = "clkp1", "clkp2", "can_clk";

		status = "disabled";

	};



	clocks {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -838,16 +858,34 @@ 
			clock-output-names = "audio_clk_c";

		};



		/* External USB clock - can be overridden by the board */

		usb_extal_clk: usb_extal_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <48000000>;

			clock-output-names = "usb_extal";

		};



		/* External CAN clock */

		can_clk: can_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			/* This value must be overridden by the board. */

			clock-frequency = <0>;

			clock-output-names = "can_clk";

			status = "disabled";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@e6150000 {

			compatible = "renesas,r8a7790-cpg-clocks",

				     "renesas,rcar-gen2-cpg-clocks";

			reg = <0 0xe6150000 0 0x1000>;

			clocks = <&extal_clk>;

			clocks = <&extal_clk &usb_extal_clk>;

			#clock-cells = <1>;

			clock-output-names = "main", "pll0", "pll1", "pll3",

					     "lb", "qspi", "sdh", "sd0", "sd1",

					     "z";

					     "z", "rcan", "adsp";

		};



		/* Variable factor clocks */
@@ -1121,13 +1159,16 @@ 
		mstp5_clks: mstp5_clks@e6150144 {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;

			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;

			clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,

				 <&extal_clk>, <&p_clk>;

			#clock-cells = <1>;

			clock-indices = <

				R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1

				R8A7790_CLK_THERMAL R8A7790_CLK_PWM

				R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL

				R8A7790_CLK_PWM

			>;

			clock-output-names = "audmac0", "audmac1", "thermal", "pwm";

			clock-output-names = "audmac0", "audmac1", "adsp_mod",

					     "thermal", "pwm";

		};

		mstp7_clks: mstp7_clks@e615014c {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1465,4 +1506,55 @@ 
			ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };

		};

	};



	ipmmu_sy0: mmu@e6280000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xe6280000 0 0x1000>;

		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,

			     <0 224 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};



	ipmmu_sy1: mmu@e6290000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xe6290000 0 0x1000>;

		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};



	ipmmu_ds: mmu@e6740000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xe6740000 0 0x1000>;

		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,

			     <0 199 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};



	ipmmu_mp: mmu@ec680000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xec680000 0 0x1000>;

		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};



	ipmmu_mx: mmu@fe951000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xfe951000 0 0x1000>;

		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,

			     <0 221 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};



	ipmmu_rt: mmu@ffc80000 {

		compatible = "renesas,ipmmu-vmsa";

		reg = <0 0xffc80000 0 0x1000>;

		interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		status = "disabled";

	};

};

arch/arm/boot/dts/r8a7791-henninger.dts

+11 −0
Original line number Diff line number Diff line
@@ -141,6 +141,11 @@ 
		renesas,groups = "vin0_data8", "vin0_clk";

		renesas,function = "vin0";

	};



	can0_pins: can0 {

		renesas,groups = "can0_data";

		renesas,function = "can0";

	};

};



&scif0 {
@@ -307,3 +312,9 @@ 
		};

	};

};



&can0 {

	pinctrl-0 = <&can0_pins>;

	pinctrl-names = "default";

	status = "okay";

};