Loading drivers/clk/qcom/clk-rpmh.c +3 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,7 @@ static const struct clk_rpmh_desc clk_rpmh_kona = { }; DEFINE_CLK_RPMH_ARC(lito, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_VRM(lito, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(lito, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); DEFINE_CLK_RPMH_VRM(lito, rf_clk1, rf_clk1_ao, "rfclkd1", 1); DEFINE_CLK_RPMH_VRM(lito, rf_clk2, rf_clk2_ao, "rfclkd2", 1); Loading @@ -291,6 +292,8 @@ DEFINE_CLK_RPMH_VRM(lito, rf_clk4, rf_clk4_ao, "rfclkd4", 1); static struct clk_hw *lito_rpmh_clocks[] = { [RPMH_CXO_CLK] = &lito_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &lito_bi_tcxo_ao.hw, [RPMH_LN_BB_CLK2] = &lito_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &lito_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &lito_ln_bb_clk3.hw, [RPMH_LN_BB_CLK3_A] = &lito_ln_bb_clk3_ao.hw, [RPMH_RF_CLK1] = &lito_rf_clk1.hw, Loading Loading
drivers/clk/qcom/clk-rpmh.c +3 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,7 @@ static const struct clk_rpmh_desc clk_rpmh_kona = { }; DEFINE_CLK_RPMH_ARC(lito, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_VRM(lito, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(lito, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); DEFINE_CLK_RPMH_VRM(lito, rf_clk1, rf_clk1_ao, "rfclkd1", 1); DEFINE_CLK_RPMH_VRM(lito, rf_clk2, rf_clk2_ao, "rfclkd2", 1); Loading @@ -291,6 +292,8 @@ DEFINE_CLK_RPMH_VRM(lito, rf_clk4, rf_clk4_ao, "rfclkd4", 1); static struct clk_hw *lito_rpmh_clocks[] = { [RPMH_CXO_CLK] = &lito_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &lito_bi_tcxo_ao.hw, [RPMH_LN_BB_CLK2] = &lito_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &lito_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &lito_ln_bb_clk3.hw, [RPMH_LN_BB_CLK3_A] = &lito_ln_bb_clk3_ao.hw, [RPMH_RF_CLK1] = &lito_rf_clk1.hw, Loading