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Commit 993495ae authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Rework the FBC interval/stall stuff a bit 



Don't touch DPFC_RECOMP_CTL on FBC2, use RMW to update
the FBC_CONTROL on FBC1 to make it easier for people to
experiment with different numbers. Also fix the interval
mask for FBC1.

v2: Rebased

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fd70d52a

drivers/gpu/drm/i915/i915_drv.h

+1 −2
Original line number Original line Diff line number Diff line
@@ -372,7 +372,7 @@ struct dpll; 




struct drm_i915_display_funcs {

struct drm_i915_display_funcs {

	bool (*fbc_enabled)(struct drm_device *dev);

	bool (*fbc_enabled)(struct drm_device *dev);

	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);

	void (*enable_fbc)(struct drm_crtc *crtc);

	void (*disable_fbc)(struct drm_device *dev);

	void (*disable_fbc)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_fifo_size)(struct drm_device *dev, int plane);

	int (*get_fifo_size)(struct drm_device *dev, int plane);
@@ -695,7 +695,6 @@ struct i915_fbc { 
		struct delayed_work work;

		struct delayed_work work;

		struct drm_crtc *crtc;

		struct drm_crtc *crtc;

		struct drm_framebuffer *fb;

		struct drm_framebuffer *fb;

		int interval;

	} *fbc_work;

	} *fbc_work;





	enum no_fbc_reason {

	enum no_fbc_reason {

drivers/gpu/drm/i915/intel_pm.c

+14 −20
Original line number Original line Diff line number Diff line
@@ -88,7 +88,7 @@ static void i8xx_disable_fbc(struct drm_device *dev) 
	DRM_DEBUG_KMS("disabled FBC\n");

	DRM_DEBUG_KMS("disabled FBC\n");

}

}





static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

static void i8xx_enable_fbc(struct drm_crtc *crtc)

{

{

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -126,11 +126,12 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	}

	}





	/* enable it... */

	/* enable it... */

	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;

	fbc_ctl = I915_READ(FBC_CONTROL);

	fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;

	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;

	if (IS_I945GM(dev))

	if (IS_I945GM(dev))

		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */

		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */

	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;

	fbc_ctl |= obj->fence_reg;

	fbc_ctl |= obj->fence_reg;

	I915_WRITE(FBC_CONTROL, fbc_ctl);

	I915_WRITE(FBC_CONTROL, fbc_ctl);
@@ -145,7 +146,7 @@ static bool i8xx_fbc_enabled(struct drm_device *dev) 
	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;

	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;

}

}





static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

static void g4x_enable_fbc(struct drm_crtc *crtc)

{

{

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -154,16 +155,12 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	struct drm_i915_gem_object *obj = intel_fb->obj;

	struct drm_i915_gem_object *obj = intel_fb->obj;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

	unsigned long stall_watermark = 200;

	u32 dpfc_ctl;

	u32 dpfc_ctl;





	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;

	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;

	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;

	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;

	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);

	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);





	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);





	/* enable it... */

	/* enable it... */
@@ -219,7 +216,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) 
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);

}

}





static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

static void ironlake_enable_fbc(struct drm_crtc *crtc)

{

{

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -228,7 +225,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	struct drm_i915_gem_object *obj = intel_fb->obj;

	struct drm_i915_gem_object *obj = intel_fb->obj;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

	unsigned long stall_watermark = 200;

	u32 dpfc_ctl;

	u32 dpfc_ctl;





	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);

	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
@@ -241,9 +237,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		dpfc_ctl |= obj->fence_reg;

		dpfc_ctl |= obj->fence_reg;

	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);

	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);





	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);

	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);

	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);

	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);

	/* enable it... */

	/* enable it... */
@@ -281,7 +274,7 @@ static bool ironlake_fbc_enabled(struct drm_device *dev) 
	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;

	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;

}

}





static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

static void gen7_enable_fbc(struct drm_crtc *crtc)

{

{

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -338,8 +331,7 @@ static void intel_fbc_work_fn(struct work_struct *__work) 
		 * the prior work.

		 * the prior work.

		 */

		 */

		if (work->crtc->fb == work->fb) {

		if (work->crtc->fb == work->fb) {

			dev_priv->display.enable_fbc(work->crtc,

			dev_priv->display.enable_fbc(work->crtc);

						     work->interval);





			dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;

			dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;

			dev_priv->fbc.fb_id = work->crtc->fb->base.id;

			dev_priv->fbc.fb_id = work->crtc->fb->base.id;
@@ -376,7 +368,7 @@ static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 
	dev_priv->fbc.fbc_work = NULL;

	dev_priv->fbc.fbc_work = NULL;

}

}





static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

static void intel_enable_fbc(struct drm_crtc *crtc)

{

{

	struct intel_fbc_work *work;

	struct intel_fbc_work *work;

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;
@@ -390,13 +382,12 @@ static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	work = kzalloc(sizeof(*work), GFP_KERNEL);

	work = kzalloc(sizeof(*work), GFP_KERNEL);

	if (work == NULL) {

	if (work == NULL) {

		DRM_ERROR("Failed to allocate FBC work structure\n");

		DRM_ERROR("Failed to allocate FBC work structure\n");

		dev_priv->display.enable_fbc(crtc, interval);

		dev_priv->display.enable_fbc(crtc);

		return;

		return;

	}

	}





	work->crtc = crtc;

	work->crtc = crtc;

	work->fb = crtc->fb;

	work->fb = crtc->fb;

	work->interval = interval;

	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);





	dev_priv->fbc.fbc_work = work;

	dev_priv->fbc.fbc_work = work;
@@ -611,7 +602,7 @@ void intel_update_fbc(struct drm_device *dev) 
		intel_disable_fbc(dev);

		intel_disable_fbc(dev);

	}

	}





	intel_enable_fbc(crtc, 500);

	intel_enable_fbc(crtc);

	dev_priv->fbc.no_fbc_reason = FBC_OK;

	dev_priv->fbc.no_fbc_reason = FBC_OK;

	return;

	return;
@@ -6073,6 +6064,9 @@ void intel_init_pm(struct drm_device *dev) 
			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;

			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;

			dev_priv->display.enable_fbc = i8xx_enable_fbc;

			dev_priv->display.enable_fbc = i8xx_enable_fbc;

			dev_priv->display.disable_fbc = i8xx_disable_fbc;

			dev_priv->display.disable_fbc = i8xx_disable_fbc;



			/* This value was pulled out of someone's hat */

			I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);

		}

		}

	}

	}