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Commit 99326ee3 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: program display clock on cache match 



[Why]
We seem to have an issue where high enough display clock
will not get set properly during S3 resume if we only
call vbios once

[How]
Expand condition of display clock programming to happen
even when cached display clock matches requested display
clock

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fb7b11e1

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+3 −1
Original line number Diff line number Diff line
@@ -625,7 +625,9 @@ static void dcn1_update_clocks(struct dccg *dccg, 
	}



	/* dcn1 dppclk is tied to dispclk */

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {

	/* program dispclk on = as a w/a for sleep resume clock ramping issues */

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)

			|| new_clocks->dispclk_khz == dccg->clks.dispclk_khz) {

		dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);

		dccg->clks.dispclk_khz = new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+2 −0
Original line number Diff line number Diff line
@@ -1089,6 +1089,8 @@ static void dcn10_init_hw(struct dc *dc) 
	}



	enable_power_gating_plane(dc->hwseq, true);



	memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));

}



static void reset_hw_ctx_wrap(