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Commit 98560bd8 authored by Jesper Nilsson's avatar Jesper Nilsson
Browse files

CRIS: Add more delays in DDR setup 



Also, make DDR latency configurable.

Signed-off-by: default avatarJesper Nilsson <jesper.nilsson@axis.com>
parent 2d0503d1

arch/cris/arch-v32/mach-a3/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -33,6 +33,10 @@ config ETRAX_DDR2_CONFIG 
	hex "DDR2 config"

	default "0"



config ETRAX_DDR2_LATENCY

	hex "DDR2 latency"

	default "0"



config ETRAX_PIO_CE0_CFG

       hex "PIO CE0 configuration"

       default "0"

arch/cris/arch-v32/mach-a3/dram_init.S

+15 −1
Original line number Diff line number Diff line
@@ -24,11 +24,21 @@ 


	;; Refer to ddr2 MDS for initialization sequence



	; 2. Wait 200us

	move.d   10000, $r2

1:	bne      1b

	subq     1, $r2



	; Start clock

	move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0

	move.d   REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1

	move.d   $r1, [$r0]



	; 2. Wait 200us

	move.d   10000, $r2

1:	bne      1b

	subq     1, $r2



	; Reset phy and start calibration

	move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0

	move.d   REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
@@ -52,6 +62,10 @@ do_cmd: 
	lslq     16, $r1

	or.d     $r3, $r1

	move.d   $r1, [$r0]

	; 2. Wait 200us

	move.d   10000, $r4

1:	bne      1b

	subq     1, $r4

	cmp.d    sdram_commands_end, $r2

	blo      command_loop

	nop
@@ -63,7 +77,7 @@ do_cmd: 


	; Set latency

	move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0

	move.d   0x13, $r1

	move.d   CONFIG_ETRAX_DDR2_LATENCY, $r1

	move.d   $r1, [$r0]



	; Set configuration

arch/cris/arch-v32/mach-a3/hw_settings.S

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
	; Register values

	.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)

	.dword CONFIG_ETRAX_DDR2_CONFIG

	.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)

	.dword CONFIG_ETRAX_DDR2_LATENCY

	.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)

	.dword CONFIG_ETRAX_DDR2_TIMING

	.dword CONFIG_ETRAX_DDR2_MRS