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Commit 9852ba6a authored by Gabor Juhos's avatar Gabor Juhos Committed by Ralf Baechle
Browse files

MIPS: ralink: mt7620: Add cpu-feature-override header 



Override certain CPU features to help GCC to optimize
the generated code. Saves about 150KB in the vmlinux
image with a generic configuration.

     text    data     bss     dec     hex filename
  3824158  134820  234192 4193170  3ffb92 vmlinux.no-override
  3664054  138804  234192 4037050  3d99ba vmlinux.override

Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5759/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 0d464968

arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h

0 → 100644
+57 −0
Original line number Diff line number Diff line 
/*

 * Ralink MT7620 specific CPU feature overrides

 *

 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>

 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 *

 * This file was derived from: include/asm-mips/cpu-features.h

 *	Copyright (C) 2003, 2004 Ralf Baechle

 *	Copyright (C) 2004 Maciej W. Rozycki

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 *

 */

#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H

#define _MT7620_CPU_FEATURE_OVERRIDES_H



#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_3k_cache	0

#define cpu_has_4k_cache	1

#define cpu_has_tx39_cache	0

#define cpu_has_sb1_cache	0

#define cpu_has_fpu		0

#define cpu_has_32fpr		0

#define cpu_has_counter		1

#define cpu_has_watch		1

#define cpu_has_divec		1



#define cpu_has_prefetch	1

#define cpu_has_ejtag		1

#define cpu_has_llsc		1



#define cpu_has_mips16		1

#define cpu_has_mdmx		0

#define cpu_has_mips3d		0

#define cpu_has_smartmips	0



#define cpu_has_mips32r1	1

#define cpu_has_mips32r2	1

#define cpu_has_mips64r1	0

#define cpu_has_mips64r2	0



#define cpu_has_dsp		1

#define cpu_has_dsp2		0

#define cpu_has_mipsmt		0



#define cpu_has_64bits		0

#define cpu_has_64bit_zero_reg	0

#define cpu_has_64bit_gp_regs	0

#define cpu_has_64bit_addresses	0



#define cpu_dcache_line_size()	32

#define cpu_icache_line_size()	32



#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */

arch/mips/ralink/Platform

+1 −0
Original line number Diff line number Diff line
@@ -26,3 +26,4 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt 
# Ralink MT7620

#

load-$(CONFIG_SOC_MT7620)	+= 0xffffffff80000000

cflags-$(CONFIG_SOC_MT7620)	+= -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620