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Commit 983b4b9d authored by Nick Hoath's avatar Nick Hoath Committed by Daniel Vetter
Browse files

drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 



Note that we also need this for skl.

Signed-off-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
[danvet: Note that we also need this for skl, requested by Imre.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent abab6311

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6738,6 +6738,7 @@ enum skl_disp_power_wells { 
#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100

#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)

#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)

#define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)

#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)



#define GEN9_HALF_SLICE_CHICKEN5	0xe188

drivers/gpu/drm/i915/intel_ringbuffer.c

+7 −0
Original line number Diff line number Diff line
@@ -1050,6 +1050,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) 
	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

			  STALL_DOP_GATING_DISABLE);



	/* WaDisableSbeCacheDispatchPortSharing:bxt */

	if (INTEL_REVID(dev) <= BXT_REVID_B0) {

		WA_SET_BIT_MASKED(

			GEN7_HALF_SLICE_CHICKEN1,

			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);

	}



	return 0;

}