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Commit 9736bfc4 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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cpufreq: qcom: Update cycle counter logic for CPUFREQ HW 



There could be cpufreq hw where accumulative cycle counters are not
supported. Add a device tree property to identify the same.

On those hardware the cycle counter needs to be read from core-0 of the
frequency domain.

Change-Id: Ib7969b2c5aaaf78f7c8359d7c417b9453e6c1f2f
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 4a3d1ca8

drivers/cpufreq/qcom-cpufreq-hw.c

+8 −2
Original line number Diff line number Diff line
@@ -18,8 +18,9 @@ 
#define CORE_COUNT_VAL(val)		(((val) & (GENMASK(18, 16))) >> 16)

#define LUT_ROW_SIZE			32

#define CLK_HW_DIV			2

#define CYCLE_CNTR_OFFSET(c, m)		((c - cpumask_first(m) + 1) * 4)



#define CYCLE_CNTR_OFFSET(c, m, acc_count)				\

			(acc_count ? ((c - cpumask_first(m) + 1) * 4) : 0)

enum {

	REG_ENABLE,

	REG_FREQ_LUT_TABLE,
@@ -31,6 +32,7 @@ enum { 
};



static unsigned int lut_row_size = LUT_ROW_SIZE;

static bool accumulative_counter;



struct cpufreq_qcom {

	struct cpufreq_frequency_table *table;
@@ -79,7 +81,8 @@ static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) 
	cpu_counter = &qcom_cpufreq_counter[cpu];

	spin_lock_irqsave(&cpu_counter->lock, flags);



	offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus);

	offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus,

					accumulative_counter);

	val = readl_relaxed_no_log(cpu_domain->reg_bases[REG_CYCLE_CNTR] +

				   offset);
@@ -360,6 +363,9 @@ static int qcom_cpu_resources_init(struct platform_device *pdev, 
		}

	}



	accumulative_counter = !of_property_read_bool(dev->of_node,

					"qcom,no-accumulative-counter");



	ret = qcom_get_related_cpus(index, &c->related_cpus);

	if (ret) {

		dev_err(dev, "Domain-%d failed to get related CPUs\n", index);