Commit 970354a3 authored Jun 26, 2020 by Krzysztof Kozlowski Committed by Greg Kroah-Hartman Jul 22, 2020

ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema



[ Upstream commit d7adfe5ffed9faa05f8926223086b101e14f700d ]

Fix dtschema validator warnings like:
    l2-cache@fffff000: $nodename:0:
        'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 2c2ac700

arch/arm/boot/dts/socfpga.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -710,7 +710,7 @@
		};
		};

		L2: l2-cache@fffef000 {
		L2: cache-controller@fffef000 {
		compatible = "arm,pl310-cache";
		reg = <0xfffef000 0x1000>;
		interrupts = <0 38 0x04>;

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -618,7 +618,7 @@
		reg = <0xffcfb100 0x80>;
		};

		L2: l2-cache@fffff000 {
		L2: cache-controller@fffff000 {
		compatible = "arm,pl310-cache";
		reg = <0xfffff000 0x1000>;
		interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;