Loading qcom/lito-coresight.dtsi +5 −3 Original line number Diff line number Diff line Loading @@ -366,15 +366,17 @@ arm,primecell-periphid = <0x000bb962>; reg = <0x6002000 0x1000>, <0x16280000 0x180000>, <0x7820f0 0x4>; reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; <0x16280000 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; coresight-name = "coresight-stm"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; nvmem-cells = <&stm_debug_fuse>; nvmem-cell-names = "debug_fuse"; port { stm_out_funnel_in0: endpoint { remote-endpoint = <&funnel_in0_in_stm>; Loading qcom/lito.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -3614,7 +3614,10 @@ feat_conf10: feat_conf10@602c { reg = <0x602c 0x4>; }; stm_debug_fuse: stm@20f0 { reg = <0x20f0 0x4>; }; }; }; Loading Loading
qcom/lito-coresight.dtsi +5 −3 Original line number Diff line number Diff line Loading @@ -366,15 +366,17 @@ arm,primecell-periphid = <0x000bb962>; reg = <0x6002000 0x1000>, <0x16280000 0x180000>, <0x7820f0 0x4>; reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; <0x16280000 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; coresight-name = "coresight-stm"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; nvmem-cells = <&stm_debug_fuse>; nvmem-cell-names = "debug_fuse"; port { stm_out_funnel_in0: endpoint { remote-endpoint = <&funnel_in0_in_stm>; Loading
qcom/lito.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -3614,7 +3614,10 @@ feat_conf10: feat_conf10@602c { reg = <0x602c 0x4>; }; stm_debug_fuse: stm@20f0 { reg = <0x20f0 0x4>; }; }; }; Loading