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Commit 9688ecad authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Limit FBC flush to post batch flush 



Don't issue the FBC nuke/cache clean command when invalidate_domains!=0.
That would indicate that we're not being called for the post-batch
flush.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f671d117

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -354,7 +354,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, 
	intel_ring_emit(ring, 0);

	intel_ring_advance(ring);



	if (flush_domains)

	if (!invalidate_domains && flush_domains)

		return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);



	return 0;
@@ -1838,7 +1838,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, 
	}

	intel_ring_advance(ring);



	if (IS_GEN7(dev) && flush)

	if (IS_GEN7(dev) && !invalidate && flush)

		return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);



	return 0;